Merge "ARM: dts: msm: Enable dtsi for USB driver on sdxhedgehog"

/*

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	usb3: ssusb@8a00000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x08a00000 0xf8c00>,

			<0x0007e000 0x400>;

		reg-names = "core_base", "ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		interrupt-parent = <&usb3>;

		interrupts = <0 1 2 3>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0x0 0xffffffff>;

		interrupt-map = <0x0 0 &intc 0 202 0

				 0x0 1 &intc 0 203 0

				 0x0 2 &intc 0 180 0

				 0x0 3 &spmi_bus 0x0 0x0 0xc4 0x0>;

		interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq",

				"pmic_id_irq";

		USB3_GDSC-supply = <&gdsc_usb30>;

		vdda33-supply = <&pmdcalifornium_l10>;

		vdda18-supply = <&pmdcalifornium_l5>;

		qcom,usb-dbm = <&dbm_1p5>;

		qcom,msm-bus,name = "usb3";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

					<61 512 0 0>, <61 676 0 0>,

					<61 512 0 680000>, <61 676 0 2400>;

		qcom,lpm-to-suspend-delay-ms = <2000>;

		clocks = <&clock_gcc clk_gcc_usb30_master_clk>,

			 <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>,

			 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb30_sleep_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;

		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

				"xo", "cfg_ahb_clk";

		qcom,core-clk-rate = <120000000>;

		qcom,dwc-usb3-msm-tx-fifo-size = <16896>;

		dwc3@8a00000 {

			compatible = "snps,dwc3";

			reg = <0x08a00000 0xcd00>;

			interrupt-parent = <&intc>;

			interrupts = <0 131 0>;

			usb-phy = <&qusb_phy>, <&ssphy>;

			tx-fifo-resize;

			snps,nominal-elastic-buffer;

			snps,is-utmi-l1-suspend;

			snps,hird-threshold = /bits/ 8 <0x0>;

			snps,bus-suspend-enable;

			snps,usb3-u1u2-disable;

			snps,disable-clk-gating;

			snps,num-gsi-evt-buffs = <0x3>;

			xhci-imod-value = <4000>;

		};

		qcom,usbbam@0x8b04000 {

			compatible = "qcom,usb-bam-msm";

			reg = <0x8b04000 0x1b000>;

			interrupt-parent = <&intc>;

			interrupts = <0 132 0>;

			qcom,bam-type = <0>;

			qcom,usb-bam-fifo-baseaddr = <0x08604000>;

			qcom,usb-bam-num-pipes = <1>;

			qcom,ignore-core-reset-ack;

			qcom,disable-clk-gating;

			qcom,usb-bam-override-threshold = <0x4001>;

			qcom,usb-bam-max-mbps-highspeed = <400>;

			qcom,usb-bam-max-mbps-superspeed = <3600>;

			qcom,reset-bam-on-connect;

			qcom,pipe0 {

				label = "ssusb-qdss-in-0";

				qcom,usb-bam-mem-type = <2>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <0>;

				qcom,peer-bam-physical-address = <0x00884000>;

				qcom,src-bam-pipe-index = <0>;

				qcom,dst-bam-pipe-index = <2>;

				qcom,data-fifo-offset = <0x0>;

				qcom,data-fifo-size = <0xc00>;

				qcom,descriptor-fifo-offset = <0xc00>;

				qcom,descriptor-fifo-size = <0x400>;

			};

		};

	};

	android_usb@86000c8 {

		compatible = "qcom,android-usb";

		reg = <0x086000c8 0xc8>;

		qcom,pm-qos-latency = <101 2001 30001>;

		qcom,supported-func = "ffs","audio","diag","serial",

			"mass_storage","rndis_gsi","ecm_gsi","rmnet_gsi",

			"mbim_gsi","dpl_gsi","gps","qdss";

	};

	qusb_phy: qusb@79000 {

		compatible = "qcom,qusb2phy-v2";

		reg = <0x79000 0x400>,

			<0x01fcb24c 0x4>;

		reg-names = "qusb_phy_base",

				"tcsr_clamp_dig_n_1p8";

		qcom,efuse-bit-pos = <16>;

		qcom,efuse-num-bits = <4>;

		vdd-supply = <&pmdcalifornium_l4>;

		vdda18-supply = <&pmdcalifornium_l5>;

		vdda33-supply = <&pmdcalifornium_l10>;

		qcom,vdd-voltage-level = <0 928000 928000>;

		qcom,qusb-phy-init-seq =

			/* <value reg_offset> */

				<0x13 0x04 /* analog_controls_two */

				0x7c 0x18c /* pll_clock_inverter */

				0x80 0x2c /* pll_cmode */

				0x0a 0x184 /* pll_lock_delay */

				0xa5 0x23c /* tune1 */

				0x09 0x240 /* tune2 */

				0x00 0x21c /* imp_ctrl1 */

				0x19 0xb4>; /* digital_timers_two */

		phy_type = "utmi";

		clocks = <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_gcc_qusb_ref_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,

			 <&clock_gcc clk_gcc_qusb2a_phy_reset>,

			 <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>;

		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk",

			"phy_reset", "iface_clk";

	};

	ssphy: ssphy@78000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0x00078000 0x9f8>,

		      <0x01947244 0x4>,

		      <0x01956044 0x4>;

		reg-names = "qmp_phy_base",

			    "vls_clamp_reg",

			    "tcsr_phy_clk_scheme_sel";

		qcom,qmp-phy-init-seq =

			/* <reg_offset,diff value, se clk, delay> */

			<0x048 0x07 0x07 0x00

			 0x080 0x14 0x1A 0x00

			 0x034 0x04 0x04 0x01

			 0x138 0x30 0x30 0x00

			 0x03c 0x02 0x02 0x00

			 0x08c 0x08 0x08 0x00

			 0x15c 0x06 0x06 0x00

			 0x164 0x01 0x01 0x00

			 0x13c 0x80 0x80 0x00

			 0x0b0 0x82 0x82 0x00

			 0x0b8 0xab 0xab 0x00

			 0x0bc 0xea 0xea 0x00

			 0x0c0 0x02 0x02 0x00

			 0x060 0x06 0x06 0x00

			 0x068 0x16 0x16 0x00

			 0x070 0x36 0x36 0x00

			 0x0dc 0x00 0x00 0x00

			 0x0d8 0x3f 0x3f 0x00

			 0x0f8 0x01 0x01 0x00

			 0x0f4 0xc9 0xc9 0x00

			 0x148 0x0a 0x0a 0x00

			 0x0a0 0x00 0x00 0x00

			 0x09c 0x34 0x34 0x00

			 0x098 0x15 0x15 0x00

			 0x154 0x00 0x00 0x00

			 0x094 0x00 0x00 0x00

			 0x0f0 0x00 0x00 0x00

			 0x00c 0x0a 0x0a 0x00

			 0x010 0x01 0x01 0x00

			 0x01c 0x31 0x31 0x00

			 0x020 0x01 0x01 0x00

			 0x014 0x00 0x00 0x00

			 0x018 0x00 0x00 0x00

			 0x024 0x85 0x85 0x00

			 0x028 0x07 0x07 0x00

			 0x4c0 0x0c 0x0c 0x00

			 0x564 0x59 0x59 0x00

			 0x430 0x0b 0x0b 0x00

			 0x4d4 0x0e 0x0e 0x00

			 0x4d8 0x4e 0x4e 0x00

			 0x4dc 0x18 0x18 0x00

			 0x4f8 0x77 0x77 0x00

			 0x4fc 0x80 0x80 0x00

			 0x504 0x03 0x03 0x00

			 0x50c 0x1a 0x1a 0x00

			 0x260 0x10 0x10 0x00

			 0x2a4 0x12 0x12 0x00

			 0x28c 0xc6 0xc6 0x00

			 0x8c8 0x83 0x83 0x00

			 0x8cc 0x09 0x09 0x00

			 0x8d0 0xa2 0xa2 0x00

			 0x8d4 0x40 0x40 0x00

			 0x8c4 0x02 0x02 0x00

			 0x880 0xd1 0xd1 0x00

			 0x884 0x1f 0x1f 0x00

			 0x888 0x47 0x47 0x00

			 0x864 0x1b 0x1b 0x00

			 0x0d0 0x80 0x80 0x00

			 0x434 0x75 0x75 0x00

			 0x43c 0x00 0x00 0x00

			 0x440 0x00 0x00 0x00

			 0x444 0x80 0x80 0x00

			 0x408 0x0a 0x0a 0x00

			 0x414 0x06 0x06 0x00

			 0x500 0x00 0x00 0x00

			 0x244 0x00 0x00 0x00

			 0x80c 0x9f 0x9f 0x00

			 0x810 0x9f 0x9f 0x00

			 0x814 0xb5 0xb5 0x00

			 0x818 0x4c 0x4c 0x00

			 0x81c 0x64 0x64 0x00

			 0x820 0x6a 0x6a 0x00

			 0x824 0x15 0x15 0x00

			 0x828 0x0d 0x0d 0x00

			 0x82c 0x15 0x15 0x00

			 0x838 0x0d 0x0d 0x00

			 0x83c 0x15 0x15 0x00

			 0x840 0x0d 0x0d 0x00

			 0x844 0x15 0x15 0x00

			 0x848 0x0d 0x0d 0x00

			 0x84c 0x15 0x15 0x00

			 0x850 0x0d 0x0d 0x00

			 0x85c 0x02 0x02 0x00

			 0x8b8 0x75 0x75 0x00

			 0x8bc 0x7a 0x7a 0x00

			 0x8b0 0x86 0x86 0x00

			 0x8a0 0x04 0x04 0x00

			 0x88c 0x44 0x44 0x00

			 0x880 0xd1 0xd1 0x00

			 0x884 0x1f 0x1f 0x00

			 0x888 0x47 0x47 0x00

			 0x870 0xf1 0xf1 0x00

			 0x874 0x01 0x01 0x00

			 0x878 0x40 0x40 0x00

			 0x87c 0x00 0x00 0x00

			 0x9d8 0xba 0xba 0x00

			 0x8b8 0x75 0x75 0x00

			 0x8b0 0x86 0x86 0x00

			 0x8bc 0x13 0x13 0x00

			 0xa0c 0x21 0x21 0x00

			 0xa10 0x60 0x60 0x00

			 0xffffffff 0xffffffff 0x00 0x00>;

		qcom,qmp-phy-reg-offset = <0x988 0x98c 0x990 0x994

					0x974 0x8d8 0x8dc 0x804 0x800

					0x808>;

		vdd-supply = <&pmdcalifornium_l4>;

		core-supply = <&pmdcalifornium_l5>;

		qcom,vdd-voltage-level = <0 928000 928000>;

		qcom,core-voltage-level = <0 1200000 1200000>;

		qcom,vbus-valid-override;

		clocks = <&clock_gcc clk_gcc_usb3_aux_clk>,

			 <&clock_gcc clk_gcc_usb3_pipe_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>,

			 <&clock_gcc clk_gcc_usb3_phy_reset>,

			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_gcc_usb_ss_ref_clk>;

		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",

			      "phy_reset", "phy_phy_reset",

			      "ref_clk_src", "ref_clk";

	};

	dbm_1p5: dbm@0x8af8000 {

		compatible = "qcom,usb-dbm-1p5";

		reg = <0x08af8000 0x300>;

		qcom,reset-ep-after-lpm-resume;

	};

};

		qcom,master-en = <1>;    /* Enable GPIO */

	};

};

#include "sdxhedgehog-usb.dtsi"