Merge "msm: qpnp-power-on: configure KPDPWR_N S2 for HARD_RESET at TWM entry" (687c0cf1) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/platform/msm/qpnp-power-on.c

+27 −14

Original line number	Diff line number	Diff line
		/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -494,6 +494,19 @@ static ssize_t qpnp_pon_dbc_store(struct device *dev,
		return size;
		}

		static struct qpnp_pon_config *
		qpnp_get_cfg(struct qpnp_pon *pon, u32 pon_type)
		{
		int i;

		for (i = 0; i < pon->num_pon_config; i++) {
		if (pon_type == pon->pon_cfg[i].pon_type)
		return &pon->pon_cfg[i];
		}

		return NULL;
		}

		static DEVICE_ATTR(debounce_us, 0664, qpnp_pon_dbc_show, qpnp_pon_dbc_store);

		#define PON_TWM_ENTRY_PBS_BIT BIT(0)
		@@ -502,6 +515,7 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
		{
		int rc;
		u16 rst_en_reg;
		struct qpnp_pon_config *cfg;

		/* Ignore the PS_HOLD reset config if TWM ENTRY is enabled */
		if (pon->support_twm_config && pon->twm_state == PMIC_TWM_ENABLE) {
		@@ -512,6 +526,18 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
		rc);
		return rc;
		}

		cfg = qpnp_get_cfg(pon, PON_KPDPWR);
		if (cfg) {
		/* configure KPDPWR_S2 to Hard reset */
		rc = qpnp_pon_masked_write(pon, cfg->s2_cntl_addr,
		QPNP_PON_S2_CNTL_TYPE_MASK,
		PON_POWER_OFF_HARD_RESET);
		if (rc < 0)
		pr_err("Unable to config KPDPWR_N S2 for hard-reset rc=%d\n",
		rc);
		}

		pr_crit("PMIC configured for TWM entry\n");
		return 0;
		}
		@@ -796,19 +822,6 @@ static int qpnp_pon_store_and_clear_warm_reset(struct qpnp_pon *pon)
		return 0;
		}

		static struct qpnp_pon_config *
		qpnp_get_cfg(struct qpnp_pon *pon, u32 pon_type)
		{
		int i;

		for (i = 0; i < pon->num_pon_config; i++) {
		if (pon_type == pon->pon_cfg[i].pon_type)
		return &pon->pon_cfg[i];
		}

		return NULL;
		}

		static int
		qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
		{