Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 68526e58 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Linus Walleij
Browse files

ARM: ux500: select L2X0 cache on ux500 



The cache controller needs to be enabled for the
cortex-a9 specific errata that are also selected
to work.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent ded547a4

arch/arm/mach-ux500/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ config UX500_SOC_COMMON 
	select ARM_ERRATA_753970

	select ARM_ERRATA_754322

	select ARM_ERRATA_764369

	select CACHE_L2X0



config UX500_SOC_DB5500

	bool