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Commit 684f7414 authored by Zhiwu Song's avatar Zhiwu Song Committed by Barry Song
Browse files

ARM: CSR: add rtc i/o bridge interface for SiRFprimaII 



The module is a bridge between the RTC clock domain and the CPU interface
clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through
this module.

Signed-off-by: default avatarZhiwu Song <zhiwu.song@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Reviewed-by: default avatarJamie Iles <jamie@jamieiles.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 858ba703

arch/arm/boot/dts/prima2-cb.dts

+1 −1
Original line number Diff line number Diff line
@@ -363,7 +363,7 @@ 
		};



		rtc-iobg {

			compatible = "sirf,prima2-rtciobg", "simple-bus";

			compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x80030000 0x10000>;

arch/arm/mach-prima2/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -3,5 +3,6 @@ obj-y += irq.o 
obj-y += clock.o

obj-y += rstc.o

obj-y += prima2.o

obj-y += rtciobrg.o

obj-$(CONFIG_DEBUG_LL) += lluart.o

obj-$(CONFIG_CACHE_L2X0) += l2x0.o

arch/arm/mach-prima2/rtciobrg.c

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+139 −0
Original line number Diff line number Diff line 
/*

 * RTC I/O Bridge interfaces for CSR SiRFprimaII

 * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module

 *

 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.

 *

 * Licensed under GPLv2 or later.

 */



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/of_platform.h>



#define SIRFSOC_CPUIOBRG_CTRL           0x00

#define SIRFSOC_CPUIOBRG_WRBE           0x04

#define SIRFSOC_CPUIOBRG_ADDR           0x08

#define SIRFSOC_CPUIOBRG_DATA           0x0c



/*

 * suspend asm codes will access this address to make system deepsleep

 * after DRAM becomes self-refresh

 */

void __iomem *sirfsoc_rtciobrg_base;

static DEFINE_SPINLOCK(rtciobrg_lock);



/*

 * symbols without lock are only used by suspend asm codes

 * and these symbols are not exported too

 */

void sirfsoc_rtc_iobrg_wait_sync(void)

{

	while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL))

		cpu_relax();

}



void sirfsoc_rtc_iobrg_besyncing(void)

{

	unsigned long flags;



	spin_lock_irqsave(&rtciobrg_lock, flags);



	sirfsoc_rtc_iobrg_wait_sync();



	spin_unlock_irqrestore(&rtciobrg_lock, flags);

}

EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing);



u32 __sirfsoc_rtc_iobrg_readl(u32 addr)

{

	sirfsoc_rtc_iobrg_wait_sync();



	writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);

	writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);

	writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);



	sirfsoc_rtc_iobrg_wait_sync();



	return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);

}



u32 sirfsoc_rtc_iobrg_readl(u32 addr)

{

	unsigned long flags, val;



	spin_lock_irqsave(&rtciobrg_lock, flags);



	val = __sirfsoc_rtc_iobrg_readl(addr);



	spin_unlock_irqrestore(&rtciobrg_lock, flags);



	return val;

}

EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl);



void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr)

{

	sirfsoc_rtc_iobrg_wait_sync();



	writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE);

	writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR);



	writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA);

}



void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)

{

	unsigned long flags;



	spin_lock_irqsave(&rtciobrg_lock, flags);



	sirfsoc_rtc_iobrg_pre_writel(val, addr);



	writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL);



	sirfsoc_rtc_iobrg_wait_sync();



	spin_unlock_irqrestore(&rtciobrg_lock, flags);

}

EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);



static const struct of_device_id rtciobrg_ids[] = {

	{ .compatible = "sirf,prima2-rtciobg" },

	{}

};



static int __devinit sirfsoc_rtciobrg_probe(struct platform_device *op)

{

	struct device_node *np = op->dev.of_node;



	sirfsoc_rtciobrg_base = of_iomap(np, 0);

	if (!sirfsoc_rtciobrg_base)

		panic("unable to map rtc iobrg registers\n");



	return 0;

}



static struct platform_driver sirfsoc_rtciobrg_driver = {

	.probe		= sirfsoc_rtciobrg_probe,

	.driver = {

		.name = "sirfsoc-rtciobrg",

		.owner = THIS_MODULE,

		.of_match_table	= rtciobrg_ids,

	},

};



static int __init sirfsoc_rtciobrg_init(void)

{

	return platform_driver_register(&sirfsoc_rtciobrg_driver);

}

postcore_initcall(sirfsoc_rtciobrg_init);



MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, "

		"Barry Song <baohua.song@csr.com>");

MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");

MODULE_LICENSE("GPL");

include/linux/rtc/sirfsoc_rtciobrg.h

0 → 100644
+18 −0
Original line number Diff line number Diff line 
/*

 * RTC I/O Bridge interfaces for CSR SiRFprimaII

 * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module

 *

 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.

 *

 * Licensed under GPLv2 or later.

 */

#ifndef _SIRFSOC_RTC_IOBRG_H_

#define _SIRFSOC_RTC_IOBRG_H_



extern void sirfsoc_rtc_iobrg_besyncing(void);



extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);



extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);



#endif