[media] drxk: Allow setting it on dynamic_clock mode (67f04617) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/media/dvb/frontends/drxk.h

+10 −7

Original line number	Diff line number	Diff line
		@@ -7,15 +7,17 @@
		/**
		* struct drxk_config - Configure the initial parameters for DRX-K
		*
		* adr: I2C Address of the DRX-K
		* parallel_ts: true means that the device uses parallel TS,
		* @adr: I2C Address of the DRX-K
		* @parallel_ts: True means that the device uses parallel TS,
		* Serial otherwise.
		* single_master: Device is on the single master mode
		* no_i2c_bridge: Don't switch the I2C bridge to talk with tuner
		* antenna_gpio: GPIO bit used to control the antenna
		* antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
		* @dynamic_clk: True means that the clock will be dynamically
		* adjusted. Static clock otherwise.
		* @single_master: Device is on the single master mode
		* @no_i2c_bridge: Don't switch the I2C bridge to talk with tuner
		* @antenna_gpio: GPIO bit used to control the antenna
		* @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
		* means that 1=DVBC, 0 = DVBT. Zero means the opposite.
		* microcode_name: Name of the firmware file with the microcode
		* @microcode_name: Name of the firmware file with the microcode
		*
		* On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
		* UIO-3.
		@@ -25,6 +27,7 @@ struct drxk_config {
		bool single_master;
		bool no_i2c_bridge;
		bool parallel_ts;
		bool dynamic_clk;

		bool antenna_dvbt;
		u16 antenna_gpio;

+9 −5

Original line number	Diff line number	Diff line
		@@ -650,9 +650,6 @@ static int init_state(struct drxk_state *state)
		u32 ulQual83 = DEFAULT_MER_83;
		u32 ulQual93 = DEFAULT_MER_93;

		u32 ulDVBTStaticTSClock = 1;
		u32 ulDVBCStaticTSClock = 1;

		u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
		u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;

		@@ -815,8 +812,7 @@ static int init_state(struct drxk_state *state)
		state->m_invertSTR = false; /* If TRUE; invert STR signals */
		state->m_invertVAL = false; /* If TRUE; invert VAL signals */
		state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
		state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
		state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);

		/* If TRUE; static MPEG clockrate will be used;
		otherwise clockrate will adapt to the bitrate of the TS */

		@@ -6390,6 +6386,14 @@ struct dvb_frontend drxk_attach(const struct drxk_config config,
		state->antenna_dvbt = config->antenna_dvbt;
		state->m_ChunkSize = config->chunk_size;

		if (config->dynamic_clk) {
		state->m_DVBTStaticCLK = 0;
		state->m_DVBCStaticCLK = 0;
		} else {
		state->m_DVBTStaticCLK = 1;
		state->m_DVBCStaticCLK = 1;
		}

		if (config->parallel_ts)
		state->m_enableParallel = true;
		else