Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 67c3bf6f authored by Deepak S's avatar Deepak S Committed by Daniel Vetter
Browse files

drm/i915: populate mem_freq/cz_clock for chv 



We need mem_freq or cz clock for freq/opcode conversion

Signed-off-by: default avatarDeepak S <deepak.s@linux.intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 74c4f62b

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -931,6 +931,7 @@ struct intel_gen6_power_mgmt { 
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */

	u8 rp1_freq;		/* "less than" RP0 power/freqency */

	u8 rp0_freq;		/* Non-overclocked max frequency. */

	u32 cz_freq;



	u32 ei_interrupt_count;

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -5538,6 +5538,12 @@ enum punit_power_well { 
						 GEN6_PM_RP_DOWN_THRESHOLD | \

						 GEN6_PM_RP_DOWN_TIMEOUT)



#define CHV_CZ_CLOCK_FREQ_MODE_200			200

#define CHV_CZ_CLOCK_FREQ_MODE_267			267

#define CHV_CZ_CLOCK_FREQ_MODE_320			320

#define CHV_CZ_CLOCK_FREQ_MODE_333			333

#define CHV_CZ_CLOCK_FREQ_MODE_400			400



#define GEN7_GT_SCRATCH_BASE			0x4F100

#define GEN7_GT_SCRATCH_REG_NUM			8

drivers/gpu/drm/i915/intel_pm.c

+29 −0
Original line number Diff line number Diff line
@@ -5700,6 +5700,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
static void cherryview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	mutex_lock(&dev_priv->rps.hw_lock);

	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);

	mutex_unlock(&dev_priv->rps.hw_lock);

	switch ((val >> 2) & 0x7) {

	case 0:

	case 1:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;

			dev_priv->mem_freq = 1600;

			break;

	case 2:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;

			dev_priv->mem_freq = 1600;

			break;

	case 3:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;

			dev_priv->mem_freq = 2000;

			break;

	case 4:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;

			dev_priv->mem_freq = 1600;

			break;

	case 5:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;

			dev_priv->mem_freq = 1600;

			break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);