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Commit 66e0155c authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Limit the operations done in the IRQ handler 



Go directly to the bits set rather than cycling through
all the bits that might be unset for the IRQ status.

Change-Id: Ica927c100734fc0a7fe684483546d9524539cd83
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent ec7db6c5

drivers/gpu/msm/adreno.c

+10 −10
Original line number Diff line number Diff line
@@ -737,23 +737,23 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device) 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_irq *irq_params = gpudev->irq;

	irqreturn_t ret = IRQ_NONE;

	unsigned int status = 0, tmp = 0;

	unsigned int status = 0, tmp;

	int i;



	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &status);



	/* Loop through all set interrupts and call respective handlers */

	for (tmp = status, i = 0; tmp &&

		 i < irq_params->funcs_count; i++) {

		if (tmp & 1) {

	for (tmp = status; tmp != 0;) {

		i = fls(tmp) - 1;



		if (irq_params->funcs[i].func != NULL) {

			irq_params->funcs[i].func(adreno_dev, i);

			ret = IRQ_HANDLED;

		} else

			KGSL_DRV_CRIT(device,

					"Unhandled interrupt bit %x\n", i);

		}

		tmp >>= 1;



		tmp &= ~BIT(i);

	}



	gpudev->irq_trace(adreno_dev, status);

drivers/gpu/msm/adreno.h

+0 −1
Original line number Diff line number Diff line
@@ -610,7 +610,6 @@ struct adreno_irq_funcs { 
struct adreno_irq {

	unsigned int mask;

	struct adreno_irq_funcs *funcs;

	int funcs_count;

};



/*

drivers/gpu/msm/adreno_a3xx.c

+1 −3
Original line number Diff line number Diff line
@@ -762,7 +762,7 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit) 
	 (1 << A3XX_INT_CP_AHB_ERROR_HALT) |     \

	 (1 << A3XX_INT_UCHE_OOB_ACCESS))



static struct adreno_irq_funcs a3xx_irq_funcs[] = {

static struct adreno_irq_funcs a3xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),                    /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a3xx_err_callback),  /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(NULL),  /* 2 - RBBM_REG_TIMEOUT */
@@ -793,12 +793,10 @@ static struct adreno_irq_funcs a3xx_irq_funcs[] = { 
	/* 24 - MISC_HANG_DETECT */

	ADRENO_IRQ_CALLBACK(adreno_hang_int_callback),

	ADRENO_IRQ_CALLBACK(a3xx_err_callback),  /* 25 - UCHE_OOB_ACCESS */

	/* 26 to 31 - Unused */

};



static struct adreno_irq a3xx_irq = {

	.funcs = a3xx_irq_funcs,

	.funcs_count = ARRAY_SIZE(a3xx_irq_funcs),

	.mask = A3XX_INT_MASK,

};

drivers/gpu/msm/adreno_a4xx.c

+1 −2
Original line number Diff line number Diff line
@@ -1741,7 +1741,7 @@ static struct adreno_coresight a4xx_coresight = { 
	 (1 << A4XX_INT_RBBM_DPM_THERMAL_RED_ERR))





static struct adreno_irq_funcs a4xx_irq_funcs[] = {

static struct adreno_irq_funcs a4xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),                   /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a4xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a4xx_err_callback), /* 2 - RBBM_REG_TIMEOUT */
@@ -1787,7 +1787,6 @@ static struct adreno_irq_funcs a4xx_irq_funcs[] = { 


static struct adreno_irq a4xx_irq = {

	.funcs = a4xx_irq_funcs,

	.funcs_count = ARRAY_SIZE(a4xx_irq_funcs),

	.mask = A4XX_INT_MASK,

};

drivers/gpu/msm/adreno_a5xx.c

+1 −2
Original line number Diff line number Diff line
@@ -2793,7 +2793,7 @@ void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit) 
	 (1 << A5XX_INT_GPMU_VOLTAGE_DROOP))





static struct adreno_irq_funcs a5xx_irq_funcs[] = {

static struct adreno_irq_funcs a5xx_irq_funcs[32] = {

	ADRENO_IRQ_CALLBACK(NULL),              /* 0 - RBBM_GPU_IDLE */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 1 - RBBM_AHB_ERROR */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback), /* 2 - RBBM_TRANSFER_TIMEOUT */
@@ -2840,7 +2840,6 @@ static struct adreno_irq_funcs a5xx_irq_funcs[] = { 


static struct adreno_irq a5xx_irq = {

	.funcs = a5xx_irq_funcs,

	.funcs_count = ARRAY_SIZE(a5xx_irq_funcs),

	.mask = A5XX_INT_MASK,

};