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Commit 66d29985 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
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MIPS: Netlogic: Merge some of XLR/XLP wakup code 



Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP.  In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.

The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.

Add support for starting XLR and XLP in 1/2/4 threads per core.

Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8da24631

arch/mips/include/asm/netlogic/common.h

+23 −3
Original line number Diff line number Diff line
@@ -38,19 +38,39 @@ 
/*

 * Common SMP definitions

 */

#define	RESET_VEC_PHYS		0x1fc00000

#define	RESET_DATA_PHYS		(RESET_VEC_PHYS + (1<<10))

#define	BOOT_THREAD_MODE	0

#define	BOOT_NMI_LOCK		4

#define	BOOT_NMI_HANDLER	8



#ifndef __ASSEMBLY__

struct irq_desc;

extern struct plat_smp_ops nlm_smp_ops;

extern char nlm_reset_entry[], nlm_reset_entry_end[];

void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);

void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);

void nlm_smp_irq_init(void);

void prom_pre_boot_secondary_cpus(void);

void nlm_boot_secondary_cpus(void);

int nlm_wakeup_secondary_cpus(u32 wakeup_mask);

void nlm_boot_smp_nmi(void);

void nlm_rmiboot_preboot(void);



static inline void

nlm_set_nmi_handler(void *handler)

{

	char *reset_data;



	reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);

	*(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;

}



/*

 * Misc.

 */

extern unsigned long nlm_common_ebase;

unsigned int nlm_get_cpu_frequency(void);



extern unsigned long nlm_common_ebase;

extern int nlm_threads_per_core;

extern uint32_t nlm_cpumask, nlm_coremask;

#endif

#endif /* _NETLOGIC_COMMON_H_ */

arch/mips/include/asm/netlogic/xlp-hal/xlp.h

+2 −5
Original line number Diff line number Diff line
@@ -35,17 +35,14 @@ 
#ifndef _NLM_HAL_XLP_H

#define _NLM_HAL_XLP_H



#define	RESET_VEC_PHYS		0x1fc00000

#define	RESET_DATA_PHYS		(RESET_VEC_PHYS + (1<<10))

#define	BOOT_THREAD_MODE	0



#define PIC_UART_0_IRQ           17

#define PIC_UART_1_IRQ           18



#ifndef __ASSEMBLY__



/* SMP support functions */

void nlm_boot_core0_siblings(void);

void xlp_boot_core0_siblings(void);

void xlp_wakeup_secondary_cpus(void);



void xlp_mmu_init(void);

void nlm_hal_init(void);

arch/mips/include/asm/netlogic/xlr/xlr.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ struct uart_port; 
unsigned int nlm_xlr_uart_in(struct uart_port *, int);

void nlm_xlr_uart_out(struct uart_port *, int, int);



/* SMP helpers */

void xlr_wakeup_secondary_cpus(void);



/* XLS B silicon "Rook" */

static inline unsigned int nlm_chip_is_xls_b(void)

arch/mips/netlogic/common/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y				+= irq.o time.o

obj-$(CONFIG_SMP)		+= smp.o

obj-$(CONFIG_SMP)		+= smp.o smpboot.o

obj-$(CONFIG_EARLY_PRINTK)	+= earlycons.o

arch/mips/netlogic/common/smp.c

+73 −2
Original line number Diff line number Diff line
@@ -47,10 +47,12 @@ 


#if defined(CONFIG_CPU_XLP)

#include <asm/netlogic/xlp-hal/iomap.h>

#include <asm/netlogic/xlp-hal/xlp.h>

#include <asm/netlogic/xlp-hal/pic.h>

#elif defined(CONFIG_CPU_XLR)

#include <asm/netlogic/xlr/iomap.h>

#include <asm/netlogic/xlr/pic.h>

#include <asm/netlogic/xlr/xlr.h>

#else

#error "Unknown CPU"

#endif
@@ -125,10 +127,10 @@ void nlm_cpus_done(void) 
 * Boot all other cpus in the system, initialize them, and bring them into

 * the boot function

 */

int nlm_cpu_unblock[NR_CPUS];

int nlm_cpu_ready[NR_CPUS];

unsigned long nlm_next_gp;

unsigned long nlm_next_sp;



cpumask_t phys_cpu_present_map;



void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -142,7 +144,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) 


	/* barrier */

	__sync();

	nlm_cpu_unblock[cpu] = 1;

	nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);

}



void __init nlm_smp_setup(void)
@@ -178,12 +180,81 @@ void __init nlm_smp_setup(void) 
		(unsigned long)cpu_possible_map.bits[0]);



	pr_info("Detected %i Slave CPU(s)\n", num_cpus);

	nlm_set_nmi_handler(nlm_boot_secondary_cpus);

}



void nlm_prepare_cpus(unsigned int max_cpus)

{

}



static int nlm_parse_cpumask(u32 cpu_mask)

{

	uint32_t core0_thr_mask, core_thr_mask;

	int threadmode, i;



	core0_thr_mask = cpu_mask & 0xf;

	switch (core0_thr_mask) {

	case 1:

		nlm_threads_per_core = 1;

		threadmode = 0;

		break;

	case 3:

		nlm_threads_per_core = 2;

		threadmode = 2;

		break;

	case 0xf:

		nlm_threads_per_core = 4;

		threadmode = 3;

		break;

	default:

		goto unsupp;

	}



	/* Verify other cores CPU masks */

	nlm_coremask = 1;

	nlm_cpumask = core0_thr_mask;

	for (i = 1; i < 8; i++) {

		core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;

		if (core_thr_mask) {

			if (core_thr_mask != core0_thr_mask)

				goto unsupp;

			nlm_coremask |= 1 << i;

			nlm_cpumask |= core0_thr_mask << (4 * i);

		}

	}

	return threadmode;



unsupp:

	panic("Unsupported CPU mask %x\n", cpu_mask);

	return 0;

}



int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)

{

	unsigned long reset_vec;

	char *reset_data;

	int threadmode;



	/* Update reset entry point with CPU init code */

	reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);

	memcpy((void *)reset_vec, (void *)nlm_reset_entry,

			(nlm_reset_entry_end - nlm_reset_entry));



	/* verify the mask and setup core config variables */

	threadmode = nlm_parse_cpumask(wakeup_mask);



	/* Setup CPU init parameters */

	reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);

	*(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;



#ifdef CONFIG_CPU_XLP

	xlp_wakeup_secondary_cpus();

#else

	xlr_wakeup_secondary_cpus();

#endif

	return 0;

}



struct plat_smp_ops nlm_smp_ops = {

	.send_ipi_single	= nlm_send_ipi_single,

	.send_ipi_mask		= nlm_send_ipi_mask,