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Commit 659fb32d authored by Simon Guinot's avatar Simon Guinot Committed by Arnd Bergmann
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genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd) 



This fixes a regression introduced by e59347a1 "arm: orion:
Use generic irq chip".

Depending on the device, interrupts acknowledgement is done by setting
or by clearing a dedicated register. Replace irq_gc_ack() with some
{set,clr}_bit variants allows to handle both cases.

Note that this patch affects the following SoCs: Davinci, Samsung and
Orion. Except for this last, the change is minor: irq_gc_ack() is just
renamed into irq_gc_ack_set_bit().

For the Orion SoCs, the edge GPIO interrupts support is currently
broken. irq_gc_ack() try to acknowledge a such interrupt by setting
the corresponding cause register bit. The Orion GPIO device expect the
opposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.

Tested on Network Space v2.

Reported-by: default avatarJoey Oravec <joravec@drewtech.com>
Signed-off-by: default avatarSimon Guinot <sguinot@lacie.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent d30e1521

arch/arm/mach-davinci/irq.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -53,7 +53,7 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 




	gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);

	gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);

	ct = gc->chip_types;

	ct = gc->chip_types;

	ct->chip.irq_ack = irq_gc_ack;

	ct->chip.irq_ack = irq_gc_ack_set_bit;

	ct->chip.irq_mask = irq_gc_mask_clr_bit;

	ct->chip.irq_mask = irq_gc_mask_clr_bit;

	ct->chip.irq_unmask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_set_bit;

arch/arm/plat-orion/gpio.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -432,7 +432,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio, 
	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;

	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;

	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;

	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;

	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;

	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;

	ct->chip.irq_ack = irq_gc_ack;

	ct->chip.irq_ack = irq_gc_ack_clr_bit;

	ct->chip.irq_mask = irq_gc_mask_clr_bit;

	ct->chip.irq_mask = irq_gc_mask_clr_bit;

	ct->chip.irq_unmask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_set_bit;

	ct->chip.irq_set_type = gpio_irq_set_type;

	ct->chip.irq_set_type = gpio_irq_set_type;

arch/arm/plat-s5p/irq-gpioint.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -152,7 +152,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) 
	if (!gc)

	if (!gc)

		return -ENOMEM;

		return -ENOMEM;

	ct = gc->chip_types;

	ct = gc->chip_types;

	ct->chip.irq_ack = irq_gc_ack;

	ct->chip.irq_ack = irq_gc_ack_set_bit;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->chip.irq_set_type = s5p_gpioint_set_type,

	ct->chip.irq_set_type = s5p_gpioint_set_type,

arch/arm/plat-samsung/irq-uart.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -55,7 +55,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) 
	gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,

	gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,

				    handle_level_irq);

				    handle_level_irq);

	ct = gc->chip_types;

	ct = gc->chip_types;

	ct->chip.irq_ack = irq_gc_ack;

	ct->chip.irq_ack = irq_gc_ack_set_bit;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->regs.ack = S3C64XX_UINTP;

	ct->regs.ack = S3C64XX_UINTP;

include/linux/irq.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -676,7 +676,8 @@ void irq_gc_mask_disable_reg(struct irq_data *d); 
void irq_gc_mask_set_bit(struct irq_data *d);

void irq_gc_mask_set_bit(struct irq_data *d);

void irq_gc_mask_clr_bit(struct irq_data *d);

void irq_gc_mask_clr_bit(struct irq_data *d);

void irq_gc_unmask_enable_reg(struct irq_data *d);

void irq_gc_unmask_enable_reg(struct irq_data *d);

void irq_gc_ack(struct irq_data *d);

void irq_gc_ack_set_bit(struct irq_data *d);

void irq_gc_ack_clr_bit(struct irq_data *d);

void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);

void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);

void irq_gc_eoi(struct irq_data *d);

void irq_gc_eoi(struct irq_data *d);

int irq_gc_set_wake(struct irq_data *d, unsigned int on);

int irq_gc_set_wake(struct irq_data *d, unsigned int on);