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Commit 657fc11c authored by Tero Kristo's avatar Tero Kristo Committed by Mike Turquette
Browse files

ARM: dts: omap3 clock data 



This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent ea291c98

arch/arm/boot/dts/am35xx-clocks.dtsi

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+128 −0
Original line number Original line Diff line number Diff line 
/*

 * Device Tree Source for OMAP3 clock data

 *

 * Copyright (C) 2013 Texas Instruments, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

&scrm_clocks {

	emac_ick: emac_ick {

		#clock-cells = <0>;

		compatible = "ti,am35xx-gate-clock";

		clocks = <&ipss_ick>;

		reg = <0x059c>;

		ti,bit-shift = <1>;

	};



	emac_fck: emac_fck {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&rmii_ck>;

		reg = <0x059c>;

		ti,bit-shift = <9>;

	};



	vpfe_ick: vpfe_ick {

		#clock-cells = <0>;

		compatible = "ti,am35xx-gate-clock";

		clocks = <&ipss_ick>;

		reg = <0x059c>;

		ti,bit-shift = <2>;

	};



	vpfe_fck: vpfe_fck {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&pclk_ck>;

		reg = <0x059c>;

		ti,bit-shift = <10>;

	};



	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {

		#clock-cells = <0>;

		compatible = "ti,am35xx-gate-clock";

		clocks = <&ipss_ick>;

		reg = <0x059c>;

		ti,bit-shift = <0>;

	};



	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&sys_ck>;

		reg = <0x059c>;

		ti,bit-shift = <8>;

	};



	hecc_ck: hecc_ck {

		#clock-cells = <0>;

		compatible = "ti,am35xx-gate-clock";

		clocks = <&sys_ck>;

		reg = <0x059c>;

		ti,bit-shift = <3>;

	};

};

&cm_clocks {

	ipss_ick: ipss_ick {

		#clock-cells = <0>;

		compatible = "ti,am35xx-interface-clock";

		clocks = <&core_l3_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <4>;

	};



	rmii_ck: rmii_ck {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <50000000>;

	};



	pclk_ck: pclk_ck {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <27000000>;

	};



	uart4_ick_am35xx: uart4_ick_am35xx {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <23>;

	};



	uart4_fck_am35xx: uart4_fck_am35xx {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&core_48m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <23>;

	};

};



&cm_clockdomains {

	core_l3_clkdm: core_l3_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,

			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,

			 <&hecc_ck>;

	};



	core_l4_clkdm: core_l4_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,

			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,

			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,

			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,

			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,

			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,

			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,

			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,

			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,

			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,

			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,

			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;

	};

};

arch/arm/boot/dts/omap3.dtsi

+41 −0
Original line number Original line Diff line number Diff line
@@ -89,6 +89,45 @@ 
			interrupts = <0>;

			interrupts = <0>;

		};

		};





		prm: prm@48306000 {

			compatible = "ti,omap3-prm";

			reg = <0x48306000 0x4000>;



			prm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			prm_clockdomains: clockdomains {

			};

		};



		cm: cm@48004000 {

			compatible = "ti,omap3-cm";

			reg = <0x48004000 0x4000>;



			cm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			cm_clockdomains: clockdomains {

			};

		};



		scrm: scrm@48002000 {

			compatible = "ti,omap3-scrm";

			reg = <0x48002000 0x2000>;



			scrm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			scrm_clockdomains: clockdomains {

			};

		};



		counter32k: counter@48320000 {

		counter32k: counter@48320000 {

			compatible = "ti,omap-counter32k";

			compatible = "ti,omap-counter32k";

			reg = <0x48320000 0x20>;

			reg = <0x48320000 0x20>;
@@ -632,3 +671,5 @@ 
		};

		};

	};

	};

};

};



/include/ "omap3xxx-clocks.dtsi"

arch/arm/boot/dts/omap3430es1-clocks.dtsi

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/*

 * Device Tree Source for OMAP3430 ES1 clock data

 *

 * Copyright (C) 2013 Texas Instruments, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

&cm_clocks {

	gfx_l3_ck: gfx_l3_ck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&l3_ick>;

		reg = <0x0b10>;

		ti,bit-shift = <0>;

	};



	gfx_l3_fck: gfx_l3_fck {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&l3_ick>;

		ti,max-div = <7>;

		reg = <0x0b40>;

		ti,index-starts-at-one;

	};



	gfx_l3_ick: gfx_l3_ick {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&gfx_l3_ck>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	gfx_cg1_ck: gfx_cg1_ck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&gfx_l3_fck>;

		reg = <0x0b00>;

		ti,bit-shift = <1>;

	};



	gfx_cg2_ck: gfx_cg2_ck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&gfx_l3_fck>;

		reg = <0x0b00>;

		ti,bit-shift = <2>;

	};



	d2d_26m_fck: d2d_26m_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&sys_ck>;

		reg = <0x0a00>;

		ti,bit-shift = <3>;

	};



	fshostusb_fck: fshostusb_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&core_48m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <5>;

	};



	ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,composite-no-wait-gate-clock";

		clocks = <&corex2_fck>;

		ti,bit-shift = <0>;

		reg = <0x0a00>;

	};



	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,composite-divider-clock";

		clocks = <&corex2_fck>;

		ti,bit-shift = <8>;

		reg = <0x0a40>;

		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;

	};



	ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;

	};



	ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&ssi_ssr_fck_3430es1>;

		clock-mult = <1>;

		clock-div = <2>;

	};



	hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,omap3-no-wait-interface-clock";

		clocks = <&core_l3_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <4>;

	};



	fac_ick: fac_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <8>;

	};



	ssi_l4_ick: ssi_l4_ick {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&l4_ick>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	ssi_ick_3430es1: ssi_ick_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,omap3-no-wait-interface-clock";

		clocks = <&ssi_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <0>;

	};



	usb_l4_gate_ick: usb_l4_gate_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-interface-clock";

		clocks = <&l4_ick>;

		ti,bit-shift = <5>;

		reg = <0x0a10>;

	};



	usb_l4_div_ick: usb_l4_div_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-divider-clock";

		clocks = <&l4_ick>;

		ti,bit-shift = <4>;

		ti,max-div = <1>;

		reg = <0x0a40>;

		ti,index-starts-at-one;

	};



	usb_l4_ick: usb_l4_ick {

		#clock-cells = <0>;

		compatible = "ti,composite-clock";

		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;

	};



	dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll4_m4x2_ck>;

		ti,bit-shift = <0>;

		reg = <0x0e00>;

		ti,set-rate-parent;

	};



	dss_ick_3430es1: dss_ick_3430es1 {

		#clock-cells = <0>;

		compatible = "ti,omap3-no-wait-interface-clock";

		clocks = <&l4_ick>;

		reg = <0x0e10>;

		ti,bit-shift = <0>;

	};

};



&cm_clockdomains {

	core_l3_clkdm: core_l3_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;

	};



	gfx_3430es1_clkdm: gfx_3430es1_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;

	};



	dss_clkdm: dss_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,

			 <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;

	};



	d2d_clkdm: d2d_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&d2d_26m_fck>;

	};



	core_l4_clkdm: core_l4_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,

			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,

			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,

			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,

			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,

			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,

			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,

			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,

			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,

			 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;

	};

};

arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi

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/*

 * Device Tree Source for OMAP34XX/OMAP36XX clock data

 *

 * Copyright (C) 2013 Texas Instruments, Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

&cm_clocks {

	security_l4_ick2: security_l4_ick2 {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&l4_ick>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	aes1_ick: aes1_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&security_l4_ick2>;

		ti,bit-shift = <3>;

		reg = <0x0a14>;

	};



	rng_ick: rng_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&security_l4_ick2>;

		reg = <0x0a14>;

		ti,bit-shift = <2>;

	};



	sha11_ick: sha11_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&security_l4_ick2>;

		reg = <0x0a14>;

		ti,bit-shift = <1>;

	};



	des1_ick: des1_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&security_l4_ick2>;

		reg = <0x0a14>;

		ti,bit-shift = <0>;

	};



	cam_mclk: cam_mclk {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&dpll4_m5x2_ck>;

		ti,bit-shift = <0>;

		reg = <0x0f00>;

		ti,set-rate-parent;

	};



	cam_ick: cam_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-no-wait-interface-clock";

		clocks = <&l4_ick>;

		reg = <0x0f10>;

		ti,bit-shift = <0>;

	};



	csi2_96m_fck: csi2_96m_fck {

		#clock-cells = <0>;

		compatible = "ti,gate-clock";

		clocks = <&core_96m_fck>;

		reg = <0x0f00>;

		ti,bit-shift = <1>;

	};



	security_l3_ick: security_l3_ick {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&l3_ick>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	pka_ick: pka_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&security_l3_ick>;

		reg = <0x0a14>;

		ti,bit-shift = <4>;

	};



	icr_ick: icr_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <29>;

	};



	des2_ick: des2_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <26>;

	};



	mspro_ick: mspro_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <23>;

	};



	mailboxes_ick: mailboxes_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&core_l4_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <7>;

	};



	ssi_l4_ick: ssi_l4_ick {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&l4_ick>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	sr1_fck: sr1_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&sys_ck>;

		reg = <0x0c00>;

		ti,bit-shift = <6>;

	};



	sr2_fck: sr2_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&sys_ck>;

		reg = <0x0c00>;

		ti,bit-shift = <7>;

	};



	sr_l4_ick: sr_l4_ick {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&l4_ick>;

		clock-mult = <1>;

		clock-div = <1>;

	};



	dpll2_fck: dpll2_fck {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&core_ck>;

		ti,bit-shift = <19>;

		ti,max-div = <7>;

		reg = <0x0040>;

		ti,index-starts-at-one;

	};



	dpll2_ck: dpll2_ck {

		#clock-cells = <0>;

		compatible = "ti,omap3-dpll-clock";

		clocks = <&sys_ck>, <&dpll2_fck>;

		reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;

		ti,low-power-stop;

		ti,lock;

		ti,low-power-bypass;

	};



	dpll2_m2_ck: dpll2_m2_ck {

		#clock-cells = <0>;

		compatible = "ti,divider-clock";

		clocks = <&dpll2_ck>;

		ti,max-div = <31>;

		reg = <0x0044>;

		ti,index-starts-at-one;

	};



	iva2_ck: iva2_ck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&dpll2_m2_ck>;

		reg = <0x0000>;

		ti,bit-shift = <0>;

	};



	modem_fck: modem_fck {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&sys_ck>;

		reg = <0x0a00>;

		ti,bit-shift = <31>;

	};



	sad2d_ick: sad2d_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&l3_ick>;

		reg = <0x0a10>;

		ti,bit-shift = <3>;

	};



	mad2d_ick: mad2d_ick {

		#clock-cells = <0>;

		compatible = "ti,omap3-interface-clock";

		clocks = <&l3_ick>;

		reg = <0x0a18>;

		ti,bit-shift = <3>;

	};



	mspro_fck: mspro_fck {

		#clock-cells = <0>;

		compatible = "ti,wait-gate-clock";

		clocks = <&core_96m_fck>;

		reg = <0x0a00>;

		ti,bit-shift = <23>;

	};

};



&cm_clockdomains {

	cam_clkdm: cam_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&cam_ick>, <&csi2_96m_fck>;

	};



	iva2_clkdm: iva2_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&iva2_ck>;

	};



	dpll2_clkdm: dpll2_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&dpll2_ck>;

	};



	wkup_clkdm: wkup_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,

			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,

			 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;

	};



	d2d_clkdm: d2d_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;

	};



	core_l4_clkdm: core_l4_clkdm {

		compatible = "ti,clockdomain";

		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,

			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,

			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,

			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,

			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,

			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,

			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,

			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,

			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,

			 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,

			 <&mspro_fck>;

	};

};

arch/arm/boot/dts/omap34xx.dtsi

+4 −0
Original line number Original line Diff line number Diff line
@@ -26,3 +26,7 @@ 
		};

		};

	};

	};

};

};



/include/ "omap34xx-omap36xx-clocks.dtsi"

/include/ "omap36xx-omap3430es2plus-clocks.dtsi"

/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
 
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