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Commit 656d79ca authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'sunxi-dt-for-3.12-2' of https://github.com/mripard/linux into next/dt 

Allwinner sunXi DT additions for 3.12, take 2

These patches add basic support for:
  - Allwinner A31 and A20 SoCs
  - The Olimex A20-Olinuxino board
  - The Olimex A10s-Olinuxino board

* tag 'sunxi-dt-for-3.12-2' of https://github.com/mripard/linux:
  ARM: sun7i: Add Olimex A20-Olinuxino-Micro support
  ARM: sun7i: Add Allwinner A20 DTSI
  ARM: sun6i: Add WITS Colombus A31 evaluation kit support
  ARM: sunxi: Add Allwinner A31 DTSI
parents 7a37ffa0 e476ac8b

arch/arm/boot/dts/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -213,7 +213,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ 
	sun4i-a10-mini-xplus.dtb \

	sun4i-a10-hackberry.dtb \

	sun5i-a10s-olinuxino-micro.dtb \

	sun5i-a13-olinuxino.dtb

	sun5i-a13-olinuxino.dtb \

	sun6i-a31-colombus.dtb \

	sun7i-a20-olinuxino-micro.dtb

dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \

	tegra20-iris-512.dtb \

	tegra20-medcom-wide.dtb \

arch/arm/boot/dts/sun6i-a31-colombus.dts

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+30 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

/include/ "sun6i-a31.dtsi"



/ {

	model = "WITS A31 Colombus Evaluation Board";

	compatible = "wits,colombus", "allwinner,sun6i-a31";



	chosen {

		bootargs = "earlyprintk console=ttyS0,115200";

	};



	soc@01c00000 {

		uart0: serial@01c28000 {

			status = "okay";

		};

	};

};

arch/arm/boot/dts/sun6i-a31.dtsi

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+156 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "skeleton.dtsi"



/ {

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

		};



		cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};



		cpu@2 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <2>;

		};



		cpu@3 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <3>;

		};

	};



	memory {

		reg = <0x40000000 0x80000000>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <0>;



		osc: oscillator {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};

	};



	soc@01c00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		timer@01c20c00 {

			compatible = "allwinner,sun4i-timer";

			reg = <0x01c20c00 0xa0>;

			interrupts = <0 18 1>,

				     <0 19 1>,

				     <0 20 1>,

				     <0 21 1>,

				     <0 22 1>;

			clocks = <&osc>;

		};



		wdt1: watchdog@01c20ca0 {

			compatible = "allwinner,sun6i-wdt";

			reg = <0x01c20ca0 0x20>;

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;

			interrupts = <0 0 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <0 1 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <0 2 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <0 3 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

			interrupts = <0 4 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		uart5: serial@01c29400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29400 0x400>;

			interrupts = <0 5 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc>;

			status = "disabled";

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,

			      <0x01c82000 0x1000>,

			      <0x01c84000 0x2000>,

			      <0x01c86000 0x2000>;

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupts = <1 9 0xf04>;

		};

	};

};

arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts

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Original line number Diff line number Diff line 
/*

 * Copyright 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

/include/ "sun7i-a20.dtsi"



/ {

	model = "Olimex A20-Olinuxino Micro";

	compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";



	soc@01c00000 {

		uart0: serial@01c28000 {

			status = "okay";

		};



		uart6: serial@01c29800 {

			status = "okay";

		};



		uart7: serial@01c29c00 {

			status = "okay";

		};

	};

};

arch/arm/boot/dts/sun7i-a20.dtsi

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+172 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/include/ "skeleton.dtsi"



/ {

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <0>;

		};



		cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};

	};



	memory {

		reg = <0x40000000 0x80000000>;

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		osc24M: osc24M@01c20050 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <24000000>;

		};



		osc32k: osc32k {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

		};

	};



	soc@01c00000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		timer@01c20c00 {

			compatible = "allwinner,sun4i-timer";

			reg = <0x01c20c00 0x90>;

			interrupts = <0 22 1>,

				     <0 23 1>,

				     <0 24 1>,

				     <0 25 1>,

				     <0 67 1>,

				     <0 68 1>;

			clocks = <&osc24M>;

		};



		wdt: watchdog@01c20c90 {

			compatible = "allwinner,sun4i-wdt";

			reg = <0x01c20c90 0x10>;

		};



		uart0: serial@01c28000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28000 0x400>;

			interrupts = <0 1 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart1: serial@01c28400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28400 0x400>;

			interrupts = <0 2 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart2: serial@01c28800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28800 0x400>;

			interrupts = <0 3 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart3: serial@01c28c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c28c00 0x400>;

			interrupts = <0 4 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart4: serial@01c29000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29000 0x400>;

			interrupts = <0 17 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart5: serial@01c29400 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29400 0x400>;

			interrupts = <0 18 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart6: serial@01c29800 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29800 0x400>;

			interrupts = <0 19 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		uart7: serial@01c29c00 {

			compatible = "snps,dw-apb-uart";

			reg = <0x01c29c00 0x400>;

			interrupts = <0 20 1>;

			reg-shift = <2>;

			reg-io-width = <4>;

			clocks = <&osc24M>;

			status = "disabled";

		};



		gic: interrupt-controller@01c81000 {

			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";

			reg = <0x01c81000 0x1000>,

			      <0x01c82000 0x1000>,

			      <0x01c84000 0x2000>,

			      <0x01c86000 0x2000>;

			interrupt-controller;

			#interrupt-cells = <3>;

			interrupts = <1 9 0xf04>;

		};

	};

};