Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6504b975 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: msm: clock-gpu-cobalt: Add the CRC programming sequence"

parents ea499e0f 52c0e20b

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -406,8 +406,9 @@ 


	clock_gpu: qcom,gpucc@5065000 {

		compatible = "qcom,gpucc-cobalt";

		reg = <0x5065000 0x9000>;

		reg-names = "cc_base";

		reg = <0x5065000 0x9000>,

			<0x50660a0 0x8>;

		reg-names = "cc_base", "crc_sid_fsm";

		vdd_gpucc-supply = <&pm8005_s1>;

		vdd_dig-supply = <&pmcobalt_s1_level>;

		vdd_mx-supply = <&pmcobalt_s9_level>;

drivers/clk/msm/clock-gpu-cobalt.c

+26 −0
Original line number Diff line number Diff line
@@ -39,6 +39,8 @@ static void __iomem *virt_base; 
#define gpu_pll0_pll_out_even_source_val	1

#define gpu_pll0_pll_out_odd_source_val		2



#define CRC_MND_CFG_OFFSET			0x4



#define F(f, s, div, m, n) \

	{ \

		.freq_hz = (f), \
@@ -393,6 +395,7 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) 
{

	struct resource *res;

	struct device_node *of_node = pdev->dev.of_node;

	void __iomem *crc_sid_fsm_ctrl;

	int rc;

	struct regulator *reg;

	u32 regval;
@@ -410,6 +413,19 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) 
		return -ENOMEM;

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crc_sid_fsm");

	if (!res) {

		dev_err(&pdev->dev, "Unable to retrieve crc_sid_fsm base\n");

		return -ENOMEM;

	}



	crc_sid_fsm_ctrl = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

	if (!crc_sid_fsm_ctrl) {

		dev_err(&pdev->dev, "Failed to map crc_sid_fsm_ctrl\n");

		return -ENOMEM;

	}



	reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");

	if (IS_ERR(reg)) {

		if (PTR_ERR(reg) != -EPROBE_DEFER)
@@ -484,6 +500,16 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) 
	 */

	clk_prepare_enable(&gpucc_cxo_clk.c);



	/* CRC ENABLE SEQUENCE */

	clk_set_rate(&gpucc_gfx3d_clk.c, 650000000);

	clk_prepare_enable(&gpucc_gfx3d_clk.c);

	/* Enabling MND RC in Bypass mode */

	writel_relaxed(0x00015010, crc_sid_fsm_ctrl + CRC_MND_CFG_OFFSET);

	writel_relaxed(0x00800000, crc_sid_fsm_ctrl);

	/* Wait for 16 cycles before continuing */

	udelay(1);

	clk_disable_unprepare(&gpucc_gfx3d_clk.c);



	dev_info(&pdev->dev, "Registered GPU clocks\n");

	return 0;

}