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Commit 65040e22 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Add XLP platform files for XLP SoC 



- Update common files to support XLP.
- Add arch/mips/include/asm/netlogic/xlp-hal for register definitions
  and access macros
- Add arch/mips/netlogic/xlp/ for XLP specific files.

Signed-off-by: default avatarJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2967/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a3d4fb2d

arch/mips/include/asm/netlogic/haldefs.h

+21 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ 
 * and will provide a way to read 32/64 bit memory mapped registers in

 * all ABIs

 */

#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)

#error "o32 compile not supported on XLP yet"

#endif

/*

 * For o32 compilation, we have to disable interrupts and enable KX bit to

 * access 64 bit addresses or data.
@@ -133,10 +136,28 @@ nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) 
/* Location where IO base is mapped */

extern uint64_t nlm_io_base;



#if defined(CONFIG_CPU_XLP)

static inline uint64_t

nlm_pcicfg_base(uint32_t devoffset)

{

	return nlm_io_base + devoffset;

}



static inline uint64_t

nlm_xkphys_map_pcibar0(uint64_t pcibase)

{

	uint64_t paddr;



	paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;

	return (uint64_t)0x9000000000000000 | paddr;

}

#elif defined(CONFIG_CPU_XLR)



static inline uint64_t

nlm_mmio_base(uint32_t devoffset)

{

	return nlm_io_base + devoffset;

}

#endif



#endif

arch/mips/include/asm/netlogic/xlp-hal/bridge.h

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Original line number Diff line number Diff line 
/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __NLM_HAL_BRIDGE_H__

#define __NLM_HAL_BRIDGE_H__



/**

* @file_name mio.h

* @author Netlogic Microsystems

* @brief Basic definitions of XLP memory and io subsystem

*/



/*

 * BRIDGE specific registers

 *

 * These registers start after the PCIe header, which has 0x40

 * standard entries

 */

#define BRIDGE_MODE			0x00

#define BRIDGE_PCI_CFG_BASE		0x01

#define BRIDGE_PCI_CFG_LIMIT		0x02

#define BRIDGE_PCIE_CFG_BASE		0x03

#define BRIDGE_PCIE_CFG_LIMIT		0x04

#define BRIDGE_BUSNUM_BAR0		0x05

#define BRIDGE_BUSNUM_BAR1		0x06

#define BRIDGE_BUSNUM_BAR2		0x07

#define BRIDGE_BUSNUM_BAR3		0x08

#define BRIDGE_BUSNUM_BAR4		0x09

#define BRIDGE_BUSNUM_BAR5		0x0a

#define BRIDGE_BUSNUM_BAR6		0x0b

#define BRIDGE_FLASH_BAR0		0x0c

#define BRIDGE_FLASH_BAR1		0x0d

#define BRIDGE_FLASH_BAR2		0x0e

#define BRIDGE_FLASH_BAR3		0x0f

#define BRIDGE_FLASH_LIMIT0		0x10

#define BRIDGE_FLASH_LIMIT1		0x11

#define BRIDGE_FLASH_LIMIT2		0x12

#define BRIDGE_FLASH_LIMIT3		0x13



#define BRIDGE_DRAM_BAR(i)		(0x14 + (i))

#define BRIDGE_DRAM_BAR0		0x14

#define BRIDGE_DRAM_BAR1		0x15

#define BRIDGE_DRAM_BAR2		0x16

#define BRIDGE_DRAM_BAR3		0x17

#define BRIDGE_DRAM_BAR4		0x18

#define BRIDGE_DRAM_BAR5		0x19

#define BRIDGE_DRAM_BAR6		0x1a

#define BRIDGE_DRAM_BAR7		0x1b



#define BRIDGE_DRAM_LIMIT(i)		(0x1c + (i))

#define BRIDGE_DRAM_LIMIT0		0x1c

#define BRIDGE_DRAM_LIMIT1		0x1d

#define BRIDGE_DRAM_LIMIT2		0x1e

#define BRIDGE_DRAM_LIMIT3		0x1f

#define BRIDGE_DRAM_LIMIT4		0x20

#define BRIDGE_DRAM_LIMIT5		0x21

#define BRIDGE_DRAM_LIMIT6		0x22

#define BRIDGE_DRAM_LIMIT7		0x23



#define BRIDGE_DRAM_NODE_TRANSLN0	0x24

#define BRIDGE_DRAM_NODE_TRANSLN1	0x25

#define BRIDGE_DRAM_NODE_TRANSLN2	0x26

#define BRIDGE_DRAM_NODE_TRANSLN3	0x27

#define BRIDGE_DRAM_NODE_TRANSLN4	0x28

#define BRIDGE_DRAM_NODE_TRANSLN5	0x29

#define BRIDGE_DRAM_NODE_TRANSLN6	0x2a

#define BRIDGE_DRAM_NODE_TRANSLN7	0x2b

#define BRIDGE_DRAM_CHNL_TRANSLN0	0x2c

#define BRIDGE_DRAM_CHNL_TRANSLN1	0x2d

#define BRIDGE_DRAM_CHNL_TRANSLN2	0x2e

#define BRIDGE_DRAM_CHNL_TRANSLN3	0x2f

#define BRIDGE_DRAM_CHNL_TRANSLN4	0x30

#define BRIDGE_DRAM_CHNL_TRANSLN5	0x31

#define BRIDGE_DRAM_CHNL_TRANSLN6	0x32

#define BRIDGE_DRAM_CHNL_TRANSLN7	0x33

#define BRIDGE_PCIEMEM_BASE0		0x34

#define BRIDGE_PCIEMEM_BASE1		0x35

#define BRIDGE_PCIEMEM_BASE2		0x36

#define BRIDGE_PCIEMEM_BASE3		0x37

#define BRIDGE_PCIEMEM_LIMIT0		0x38

#define BRIDGE_PCIEMEM_LIMIT1		0x39

#define BRIDGE_PCIEMEM_LIMIT2		0x3a

#define BRIDGE_PCIEMEM_LIMIT3		0x3b

#define BRIDGE_PCIEIO_BASE0		0x3c

#define BRIDGE_PCIEIO_BASE1		0x3d

#define BRIDGE_PCIEIO_BASE2		0x3e

#define BRIDGE_PCIEIO_BASE3		0x3f

#define BRIDGE_PCIEIO_LIMIT0		0x40

#define BRIDGE_PCIEIO_LIMIT1		0x41

#define BRIDGE_PCIEIO_LIMIT2		0x42

#define BRIDGE_PCIEIO_LIMIT3		0x43

#define BRIDGE_PCIEMEM_BASE4		0x44

#define BRIDGE_PCIEMEM_BASE5		0x45

#define BRIDGE_PCIEMEM_BASE6		0x46

#define BRIDGE_PCIEMEM_LIMIT4		0x47

#define BRIDGE_PCIEMEM_LIMIT5		0x48

#define BRIDGE_PCIEMEM_LIMIT6		0x49

#define BRIDGE_PCIEIO_BASE4		0x4a

#define BRIDGE_PCIEIO_BASE5		0x4b

#define BRIDGE_PCIEIO_BASE6		0x4c

#define BRIDGE_PCIEIO_LIMIT4		0x4d

#define BRIDGE_PCIEIO_LIMIT5		0x4e

#define BRIDGE_PCIEIO_LIMIT6		0x4f

#define BRIDGE_NBU_EVENT_CNT_CTL	0x50

#define BRIDGE_EVNTCTR1_LOW		0x51

#define BRIDGE_EVNTCTR1_HI		0x52

#define BRIDGE_EVNT_CNT_CTL2		0x53

#define BRIDGE_EVNTCTR2_LOW		0x54

#define BRIDGE_EVNTCTR2_HI		0x55

#define BRIDGE_TRACEBUF_MATCH0		0x56

#define BRIDGE_TRACEBUF_MATCH1		0x57

#define BRIDGE_TRACEBUF_MATCH_LOW	0x58

#define BRIDGE_TRACEBUF_MATCH_HI	0x59

#define BRIDGE_TRACEBUF_CTRL		0x5a

#define BRIDGE_TRACEBUF_INIT		0x5b

#define BRIDGE_TRACEBUF_ACCESS		0x5c

#define BRIDGE_TRACEBUF_READ_DATA0	0x5d

#define BRIDGE_TRACEBUF_READ_DATA1	0x5d

#define BRIDGE_TRACEBUF_READ_DATA2	0x5f

#define BRIDGE_TRACEBUF_READ_DATA3	0x60

#define BRIDGE_TRACEBUF_STATUS		0x61

#define BRIDGE_ADDRESS_ERROR0		0x62

#define BRIDGE_ADDRESS_ERROR1		0x63

#define BRIDGE_ADDRESS_ERROR2		0x64

#define BRIDGE_TAG_ECC_ADDR_ERROR0	0x65

#define BRIDGE_TAG_ECC_ADDR_ERROR1	0x66

#define BRIDGE_TAG_ECC_ADDR_ERROR2	0x67

#define BRIDGE_LINE_FLUSH0		0x68

#define BRIDGE_LINE_FLUSH1		0x69

#define BRIDGE_NODE_ID			0x6a

#define BRIDGE_ERROR_INTERRUPT_EN	0x6b

#define BRIDGE_PCIE0_WEIGHT		0x2c0

#define BRIDGE_PCIE1_WEIGHT		0x2c1

#define BRIDGE_PCIE2_WEIGHT		0x2c2

#define BRIDGE_PCIE3_WEIGHT		0x2c3

#define BRIDGE_USB_WEIGHT		0x2c4

#define BRIDGE_NET_WEIGHT		0x2c5

#define BRIDGE_POE_WEIGHT		0x2c6

#define BRIDGE_CMS_WEIGHT		0x2c7

#define BRIDGE_DMAENG_WEIGHT		0x2c8

#define BRIDGE_SEC_WEIGHT		0x2c9

#define BRIDGE_COMP_WEIGHT		0x2ca

#define BRIDGE_GIO_WEIGHT		0x2cb

#define BRIDGE_FLASH_WEIGHT		0x2cc



#ifndef __ASSEMBLY__



#define nlm_read_bridge_reg(b, r)	nlm_read_reg(b, r)

#define nlm_write_bridge_reg(b, r, v)	nlm_write_reg(b, r, v)

#define	nlm_get_bridge_pcibase(node)	\

			nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))

#define	nlm_get_bridge_regbase(node)	\

			(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)



#endif /* __ASSEMBLY__ */

#endif /* __NLM_HAL_BRIDGE_H__ */

arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h

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Original line number Diff line number Diff line 
/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __NLM_HAL_CPUCONTROL_H__

#define __NLM_HAL_CPUCONTROL_H__



#define CPU_BLOCKID_IFU		0

#define CPU_BLOCKID_ICU		1

#define CPU_BLOCKID_IEU		2

#define CPU_BLOCKID_LSU		3

#define CPU_BLOCKID_MMU		4

#define CPU_BLOCKID_PRF		5

#define CPU_BLOCKID_SCH		7

#define CPU_BLOCKID_SCU		8

#define CPU_BLOCKID_FPU		9

#define CPU_BLOCKID_MAP		10



#define LSU_DEFEATURE		0x304

#define LSU_CERRLOG_REGID	0x09

#define SCHED_DEFEATURE		0x700



/* Offsets of interest from the 'MAP' Block */

#define MAP_THREADMODE			0x00

#define MAP_EXT_EBASE_ENABLE		0x04

#define MAP_CCDI_CONFIG			0x08

#define MAP_THRD0_CCDI_STATUS		0x0c

#define MAP_THRD1_CCDI_STATUS		0x10

#define MAP_THRD2_CCDI_STATUS		0x14

#define MAP_THRD3_CCDI_STATUS		0x18

#define MAP_THRD0_DEBUG_MODE		0x1c

#define MAP_THRD1_DEBUG_MODE		0x20

#define MAP_THRD2_DEBUG_MODE		0x24

#define MAP_THRD3_DEBUG_MODE		0x28

#define MAP_MISC_STATE			0x60

#define MAP_DEBUG_READ_CTL		0x64

#define MAP_DEBUG_READ_REG0		0x68

#define MAP_DEBUG_READ_REG1		0x6c



#define MMU_SETUP		0x400

#define MMU_LFSRSEED		0x401

#define MMU_HPW_NUM_PAGE_LVL	0x410

#define MMU_PGWKR_PGDBASE	0x411

#define MMU_PGWKR_PGDSHFT	0x412

#define MMU_PGWKR_PGDMASK	0x413

#define MMU_PGWKR_PUDSHFT	0x414

#define MMU_PGWKR_PUDMASK	0x415

#define MMU_PGWKR_PMDSHFT	0x416

#define MMU_PGWKR_PMDMASK	0x417

#define MMU_PGWKR_PTESHFT	0x418

#define MMU_PGWKR_PTEMASK	0x419



#endif /* __NLM_CPUCONTROL_H__ */

arch/mips/include/asm/netlogic/xlp-hal/iomap.h

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Original line number Diff line number Diff line 
/*

 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights

 * reserved.

 *

 * This software is available to you under a choice of one of two

 * licenses.  You may choose to be licensed under the terms of the GNU

 * General Public License (GPL) Version 2, available from the file

 * COPYING in the main directory of this source tree, or the NetLogic

 * license below:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in

 *    the documentation and/or other materials provided with the

 *    distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE

 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR

 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,

 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE

 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN

 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



#ifndef __NLM_HAL_IOMAP_H__

#define __NLM_HAL_IOMAP_H__



#define XLP_DEFAULT_IO_BASE             0x18000000

#define NMI_BASE			0xbfc00000

#define	XLP_IO_CLK			133333333



#define XLP_PCIE_CFG_SIZE		0x1000		/* 4K */

#define XLP_PCIE_DEV_BLK_SIZE		(8 * XLP_PCIE_CFG_SIZE)

#define XLP_PCIE_BUS_BLK_SIZE		(256 * XLP_PCIE_DEV_BLK_SIZE)

#define XLP_IO_SIZE			(64 << 20)	/* ECFG space size */

#define XLP_IO_PCI_HDRSZ		0x100

#define XLP_IO_DEV(node, dev)		((dev) + (node) * 8)

#define XLP_HDR_OFFSET(node, bus, dev, fn)	(((bus) << 20) | \

				((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))



#define XLP_IO_BRIDGE_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 0)

/* coherent inter chip */

#define XLP_IO_CIC0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 1)

#define XLP_IO_CIC1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 2)

#define XLP_IO_CIC2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 3)

#define XLP_IO_PIC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 0, 4)



#define XLP_IO_PCIE_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 1, i)

#define XLP_IO_PCIE0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 0)

#define XLP_IO_PCIE1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 1)

#define XLP_IO_PCIE2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 2)

#define XLP_IO_PCIE3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 3)



#define XLP_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 2, i)

#define XLP_IO_USB_EHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 0)

#define XLP_IO_USB_OHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 1)

#define XLP_IO_USB_OHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 2)

#define XLP_IO_USB_EHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 3)

#define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)

#define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)



#define XLP_IO_NAE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 0)

#define XLP_IO_POE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 1)



#define XLP_IO_CMS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 4, 0)



#define XLP_IO_DMA_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 1)

#define XLP_IO_SEC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 2)

#define XLP_IO_CMP_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 3)



#define XLP_IO_UART_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 6, i)

#define XLP_IO_UART0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 0)

#define XLP_IO_UART1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 1)

#define XLP_IO_I2C_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 6, 2 + i)

#define XLP_IO_I2C0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 2)

#define XLP_IO_I2C1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 3)

#define XLP_IO_GPIO_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 4)

/* system management */

#define XLP_IO_SYS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 6, 5)

#define XLP_IO_JTAG_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 6)



#define XLP_IO_NOR_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 0)

#define XLP_IO_NAND_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 7, 1)

#define XLP_IO_SPI_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 2)

/* SD flash */

#define XLP_IO_SD_OFFSET(node)          XLP_HDR_OFFSET(node, 0, 7, 3)

#define XLP_IO_MMC_OFFSET(node, slot)   \

		((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)



/* PCI config header register id's */

#define XLP_PCI_CFGREG0			0x00

#define XLP_PCI_CFGREG1			0x01

#define XLP_PCI_CFGREG2			0x02

#define XLP_PCI_CFGREG3			0x03

#define XLP_PCI_CFGREG4			0x04

#define XLP_PCI_CFGREG5			0x05

#define XLP_PCI_DEVINFO_REG0		0x30

#define XLP_PCI_DEVINFO_REG1		0x31

#define XLP_PCI_DEVINFO_REG2		0x32

#define XLP_PCI_DEVINFO_REG3		0x33

#define XLP_PCI_DEVINFO_REG4		0x34

#define XLP_PCI_DEVINFO_REG5		0x35

#define XLP_PCI_DEVINFO_REG6		0x36

#define XLP_PCI_DEVINFO_REG7		0x37

#define XLP_PCI_DEVSCRATCH_REG0		0x38

#define XLP_PCI_DEVSCRATCH_REG1		0x39

#define XLP_PCI_DEVSCRATCH_REG2		0x3a

#define XLP_PCI_DEVSCRATCH_REG3		0x3b

#define XLP_PCI_MSGSTN_REG		0x3c

#define XLP_PCI_IRTINFO_REG		0x3d

#define XLP_PCI_UCODEINFO_REG		0x3e

#define XLP_PCI_SBB_WT_REG		0x3f



/* PCI IDs for SoC device */

#define	PCI_VENDOR_NETLOGIC		0x184e



#define	PCI_DEVICE_ID_NLM_ROOT		0x1001

#define	PCI_DEVICE_ID_NLM_ICI		0x1002

#define	PCI_DEVICE_ID_NLM_PIC		0x1003

#define	PCI_DEVICE_ID_NLM_PCIE		0x1004

#define	PCI_DEVICE_ID_NLM_EHCI		0x1007

#define	PCI_DEVICE_ID_NLM_ILK		0x1008

#define	PCI_DEVICE_ID_NLM_NAE		0x1009

#define	PCI_DEVICE_ID_NLM_POE		0x100A

#define	PCI_DEVICE_ID_NLM_FMN		0x100B

#define	PCI_DEVICE_ID_NLM_RAID		0x100D

#define	PCI_DEVICE_ID_NLM_SAE		0x100D

#define	PCI_DEVICE_ID_NLM_RSA		0x100E

#define	PCI_DEVICE_ID_NLM_CMP		0x100F

#define	PCI_DEVICE_ID_NLM_UART		0x1010

#define	PCI_DEVICE_ID_NLM_I2C		0x1011

#define	PCI_DEVICE_ID_NLM_NOR		0x1015

#define	PCI_DEVICE_ID_NLM_NAND		0x1016

#define	PCI_DEVICE_ID_NLM_MMC		0x1018



#ifndef __ASSEMBLY__



#define nlm_read_pci_reg(b, r)		nlm_read_reg(b, r)

#define nlm_write_pci_reg(b, r, v)	nlm_write_reg(b, r, v)



#endif /* !__ASSEMBLY */



#endif /* __NLM_HAL_IOMAP_H__ */

arch/mips/include/asm/netlogic/xlp-hal/pic.h

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