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Commit 650158b5 authored by Lucas Stach's avatar Lucas Stach Committed by Sasha Levin
Browse files

drm/radeon: fix PLL sharing on DCE6.1 (v2) 

[ Upstream commit e3c00d87845ab375f90fa6e10a5e72a3a5778cd3 ]

On DCE6.1 PPLL2 is exclusively available to UNIPHYA, so it should not
be taken into consideration when looking for an already enabled PLL
to be shared with other outputs.

This fixes the broken VGA port (TRAVIS DP->VGA bridge) on my Richland
based laptop, where the internal display is connected to UNIPHYA through
a TRAVIS DP->LVDS bridge.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=78987



v2: agd: add check in radeon_get_shared_nondp_ppll as well, drop
    extra parameter.

Signed-off-by: default avatarLucas Stach <dev@lynxeye.de>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarSasha Levin <sasha.levin@oracle.com>
parent d0cc41a3

drivers/gpu/drm/radeon/atombios_crtc.c

+10 −0
Original line number Diff line number Diff line
@@ -1730,6 +1730,7 @@ static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct drm_crtc *test_crtc;

	struct radeon_crtc *test_radeon_crtc;
@@ -1739,6 +1740,10 @@ static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 
		test_radeon_crtc = to_radeon_crtc(test_crtc);

		if (test_radeon_crtc->encoder &&

		    ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {

			/* PPLL2 is exclusive to UNIPHYA on DCE61 */

			if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&

			    test_radeon_crtc->pll_id == ATOM_PPLL2)

				continue;

			/* for DP use the same PLL for all */

			if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)

				return test_radeon_crtc->pll_id;
@@ -1760,6 +1765,7 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 
{

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct drm_crtc *test_crtc;

	struct radeon_crtc *test_radeon_crtc;

	u32 adjusted_clock, test_adjusted_clock;
@@ -1775,6 +1781,10 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 
		test_radeon_crtc = to_radeon_crtc(test_crtc);

		if (test_radeon_crtc->encoder &&

		    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {

			/* PPLL2 is exclusive to UNIPHYA on DCE61 */

			if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&

			    test_radeon_crtc->pll_id == ATOM_PPLL2)

				continue;

			/* check if we are already driving this connector with another crtc */

			if (test_radeon_crtc->connector == radeon_crtc->connector) {

				/* if we are, return that pll */