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Commit 64e771bb authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next

parents 3a7c1ee4 9cd9130d

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+8 −0
Original line number Diff line number Diff line
@@ -944,6 +944,14 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 
	else

		reg |= (1 << 28);

	ew32(TARC(1), reg);



	/*

	 * Disable IPv6 extension header parsing because some malformed

	 * IPv6 headers can hang the Rx.

	 */

	reg = er32(RFCTL);

	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

	ew32(RFCTL, reg);

}



/**

drivers/net/ethernet/intel/e1000e/82571.c

+12 −1
Original line number Diff line number Diff line
@@ -1279,6 +1279,16 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 
		ew32(CTRL_EXT, reg);

	}



	/*

	 * Disable IPv6 extension header parsing because some malformed

	 * IPv6 headers can hang the Rx.

	 */

	if (hw->mac.type <= e1000_82573) {

		reg = er32(RFCTL);

		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

		ew32(RFCTL, reg);

	}



	/* PCI-Ex Control Registers */

	switch (hw->mac.type) {

	case e1000_82574:
@@ -2064,6 +2074,7 @@ const struct e1000_info e1000_82574_info = { 
				  | FLAG_HAS_CTRLEXT_ON_LOAD,

	.flags2			 = FLAG2_CHECK_PHY_HANG

				  | FLAG2_DISABLE_ASPM_L0S

				  | FLAG2_DISABLE_ASPM_L1

				  | FLAG2_NO_DISABLE_RX

				  | FLAG2_DMA_BURST,

	.pba			= 32,

drivers/net/ethernet/intel/e1000e/e1000.h

+10 −0
Original line number Diff line number Diff line
@@ -673,11 +673,21 @@ static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 
	return hw->phy.ops.read_reg(hw, offset, data);

}



static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)

{

	return hw->phy.ops.read_reg_locked(hw, offset, data);

}



static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)

{

	return hw->phy.ops.write_reg(hw, offset, data);

}



static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)

{

	return hw->phy.ops.write_reg_locked(hw, offset, data);

}



static inline s32 e1000_get_cable_length(struct e1000_hw *hw)

{

	return hw->phy.ops.get_cable_length(hw);

drivers/net/ethernet/intel/e1000e/ich8lan.c

+26 −28
Original line number Diff line number Diff line
@@ -304,9 +304,9 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 
	u16 phy_reg;

	u32 phy_id;



	hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);

	e1e_rphy_locked(hw, PHY_ID1, &phy_reg);

	phy_id = (u32)(phy_reg << 16);

	hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);

	e1e_rphy_locked(hw, PHY_ID2, &phy_reg);

	phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);



	if (hw->phy.id) {
@@ -1271,8 +1271,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 
		reg_addr &= PHY_REG_MASK;

		reg_addr |= phy_page;



		ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,

						    reg_data);

		ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);

		if (ret_val)

			goto release;

	}
@@ -1309,7 +1308,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 
	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */

	if (link) {

		if (hw->phy.type == e1000_phy_82578) {

			ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,

			ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,

						  &status_reg);

			if (ret_val)

				goto release;
@@ -1325,8 +1324,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 
		}



		if (hw->phy.type == e1000_phy_82577) {

			ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,

			                                          &status_reg);

			ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);

			if (ret_val)

				goto release;
@@ -1341,15 +1339,13 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 
		}



		/* Link stall fix for link up */

		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),

		                                           0x0100);

		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);

		if (ret_val)

			goto release;



	} else {

		/* Link stall fix for link down */

		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),

		                                           0x4100);

		ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);

		if (ret_val)

			goto release;

	}
@@ -1448,7 +1444,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 


	mac_reg = er32(PHY_CTRL);



	ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);

	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);

	if (ret_val)

		goto release;
@@ -1475,7 +1471,7 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 
	    !hw->phy.ops.check_reset_block(hw))

		oem_reg |= HV_OEM_BITS_RESTART_AN;



	ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);

	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);



release:

	hw->phy.ops.release(hw);
@@ -1571,11 +1567,10 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 
	ret_val = hw->phy.ops.acquire(hw);

	if (ret_val)

		return ret_val;

	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);

	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);

	if (ret_val)

		goto release;

	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,

					       phy_data & 0x00FF);

	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);

release:

	hw->phy.ops.release(hw);
@@ -1807,20 +1802,18 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 
	ret_val = hw->phy.ops.acquire(hw);

	if (ret_val)

		return ret_val;

	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,

					       I82579_MSE_THRESHOLD);

	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_THRESHOLD);

	if (ret_val)

		goto release;

	/* set MSE higher to enable link to stay up when noise is high */

	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);

	ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0034);

	if (ret_val)

		goto release;

	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,

					       I82579_MSE_LINK_DOWN);

	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, I82579_MSE_LINK_DOWN);

	if (ret_val)

		goto release;

	/* drop link after 5 times MSE threshold was reached */

	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);

	ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x0005);

release:

	hw->phy.ops.release(hw);
@@ -1995,12 +1988,10 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 
		ret_val = hw->phy.ops.acquire(hw);

		if (ret_val)

			return ret_val;

		ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,

		ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR,

					  I82579_LPI_UPDATE_TIMER);

		if (!ret_val)

			ret_val = hw->phy.ops.write_reg_locked(hw,

							       I82579_EMI_DATA,

							       0x1387);

			ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, 0x1387);

		hw->phy.ops.release(hw);

	}
@@ -3477,6 +3468,13 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 
	 */

	reg = er32(RFCTL);

	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);



	/*

	 * Disable IPv6 extension header parsing because some malformed

	 * IPv6 headers can hang the Rx.

	 */

	if (hw->mac.type == e1000_ich8lan)

		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);

	ew32(RFCTL, reg);

}

drivers/net/ethernet/intel/e1000e/netdev.c

+5 −16
Original line number Diff line number Diff line
@@ -1084,6 +1084,10 @@ static void e1000_print_hw_hang(struct work_struct *work) 
	      phy_1000t_status,

	      phy_ext_status,

	      pci_status);



	/* Suggest workaround for known h/w issue */

	if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))

		e_err("Try turning off Tx pause (flow control) via ethtool\n");

}



/**
@@ -2935,6 +2939,7 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) 
	/* Enable Extended Status in all Receive Descriptors */

	rfctl = er32(RFCTL);

	rfctl |= E1000_RFCTL_EXTEN;

	ew32(RFCTL, rfctl);



	/*

	 * 82571 and greater support packet-split where the protocol
@@ -2960,13 +2965,6 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) 
	if (adapter->rx_ps_pages) {

		u32 psrctl = 0;



		/*

		 * disable packet split support for IPv6 extension headers,

		 * because some malformed IPv6 headers can hang the Rx

		 */

		rfctl |= (E1000_RFCTL_IPV6_EX_DIS |

			  E1000_RFCTL_NEW_IPV6_EXT_DIS);



		/* Enable Packet split descriptors */

		rctl |= E1000_RCTL_DTYP_PS;
@@ -3005,7 +3003,6 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter) 
		 */

	}



	ew32(RFCTL, rfctl);

	ew32(RCTL, rctl);

	/* just started the receive unit, no need to restart */

	adapter->flags &= ~FLAG_RX_RESTART_NOW;
@@ -5275,14 +5272,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) 
		return -EINVAL;

	}



	/* 82573 Errata 17 */

	if (((adapter->hw.mac.type == e1000_82573) ||

	     (adapter->hw.mac.type == e1000_82574)) &&

	    (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {

		adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;

		e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);

	}



	while (test_and_set_bit(__E1000_RESETTING, &adapter->state))

		usleep_range(1000, 2000);

	/* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */