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Commit 64dc9e2e authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge tag 'usb-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next 



Felipe writes:

usb: patches for v3.10 merge window

Here is the big Gadget & PHY pull request. Many of us have
been really busy lately getting multiple drivers to a better
position.

Since this pull request is so large, I will divide it in sections
so it's easier to grasp what's included.

- cleanups:
	. UDC drivers no longer touch gadget->dev, that's now udc-core
		responsibility
	. Many more UDC drivers converted to usb_gadget_map/unmap_request()
	. UDC drivers no longer initialize DMA-related fields from gadget's
		device structure
	. UDC drivers don't touch gadget.dev.driver directly
	. UDC drivers don't assign gadget.dev.release directly
	. Removal of some unused DMA_ADDR_INVALID
	. Introduction of CONFIG_USB_PHY
	. All phy drivers have been moved to drivers/usb/phy and renamed to
		a common naming scheme
	. Fix PHY layer so it never returns a NULL pointer, also fix all
		callers to avoid using IS_ERR_OR_NULL()
	. Sparse fixes all over the place
	. drivers/usb/otg/ has been deleted
	. Marvel drivers (mv_udc, ehci-mv, mv_otg and mv_u3d) improved clock
		usage

- new features:
	. UDC core now provides a generic way for tracking and reporting
		UDC's state (not attached, resuming, suspended, addressed,
		default, etc)
	. twl4030-usb learned that it shouldn't be enabled during init
	. Full DT support for DWC3 has been implemented
	. ab8500-usb learned about pinctrl framework
	. nop PHY learned about DeviceTree and regulators
	. DWC3 learned about suspend/resume
	. DWC3 can now be compiled in host-only and gadget-only (as well as
		DRD) configurations
	. UVC now enables streaming endpoint based on negotiated speed
	. isp1301 now implements the PHY API properly
	. configfs-based interface for gadget drivers which will lead to
		the removal of all code which just combines functions together
		to build functional gadget drivers.
	. f_serial and f_obex were converted to new configfs interface while
		maintaining old interface around.

- non-critical fixes:
	. UVC gadget driver got fixes for Endpoint usage and stream calculation
	. ab8500-usb fixed unbalanced clock and regulator API usage
	. twl4030-usb got a fix for when OMAP3 is booted with cable connected
	. fusb300_udc got a fix for DMA usage
	. UVC got fixes for two assertions of the USB Video Class Compliance
		specification revision 1.1
	. build warning issues caused by recent addition of __must_check to
		regulator API

These are all changes which deserve a mention, all other changes are related
to these one or minor spelling fixes and other similar tasks.

Signed-of-by: default avatarFelipe Balbi <balbi@ti.com>
parents 01a60e76 9b192de6

Documentation/devicetree/bindings/usb/omap-usb.txt

+34 −6
Original line number Diff line number Diff line
@@ -8,10 +8,10 @@ OMAP MUSB GLUE 
   and disconnect.

 - multipoint : Should be "1" indicating the musb controller supports

   multipoint. This is a MUSB configuration-specific setting.

 - num_eps : Specifies the number of endpoints. This is also a

 - num-eps : Specifies the number of endpoints. This is also a

   MUSB configuration-specific setting. Should be set to "16"

 - ram_bits : Specifies the ram address size. Should be set to "12"

 - interface_type : This is a board specific setting to describe the type of

 - ram-bits : Specifies the ram address size. Should be set to "12"

 - interface-type : This is a board specific setting to describe the type of

   interface between the controller and the phy. It should be "0" or "1"

   specifying ULPI and UTMI respectively.

 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
@@ -29,18 +29,46 @@ usb_otg_hs: usb_otg_hs@4a0ab000 { 
	ti,hwmods = "usb_otg_hs";

	ti,has-mailbox;

	multipoint = <1>;

	num_eps = <16>;

	ram_bits = <12>;

	num-eps = <16>;

	ram-bits = <12>;

	ctrl-module = <&omap_control_usb>;

};



Board specific device node entry

&usb_otg_hs {

	interface_type = <1>;

	interface-type = <1>;

	mode = <3>;

	power = <50>;

};



OMAP DWC3 GLUE

 - compatible : Should be "ti,dwc3"

 - ti,hwmods : Should be "usb_otg_ss"

 - reg : Address and length of the register set for the device.

 - interrupts : The irq number of this device that is used to interrupt the

   MPU

 - #address-cells, #size-cells : Must be present if the device has sub-nodes

 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.

   It should be set to "1" for HW mode and "2" for SW mode.

 - ranges: the child address space are mapped 1:1 onto the parent address space



Sub-nodes:

The dwc3 core should be added as subnode to omap dwc3 glue.

- dwc3 :

   The binding details of dwc3 can be found in:

   Documentation/devicetree/bindings/usb/dwc3.txt



omap_dwc3 {

	compatible = "ti,dwc3";

	ti,hwmods = "usb_otg_ss";

	reg = <0x4a020000 0x1ff>;

	interrupts = <0 93 4>;

	#address-cells = <1>;

	#size-cells = <1>;

	utmi-mode = <2>;

	ranges;

};



OMAP CONTROL USB



Required properties:

Documentation/devicetree/bindings/usb/samsung-usbphy.txt

+69 −7
Original line number Diff line number Diff line 
* Samsung's usb phy transceiver

SAMSUNG USB-PHY controllers



The Samsung's phy transceiver is used for controlling usb phy for

s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers

across Samsung SOCs.

** Samsung's usb 2.0 phy transceiver



The Samsung's usb 2.0 phy transceiver is used for controlling

usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos

usb controllers across Samsung SOCs.

TODO: Adding the PHY binding with controller(s) according to the under

developement generic PHY driver.



Required properties:



Exynos4210:

- compatible : should be "samsung,exynos4210-usbphy"

- compatible : should be "samsung,exynos4210-usb2phy"

- reg : base physical address of the phy registers and length of memory mapped

	region.

- clocks: Clock IDs array as required by the controller.

- clock-names: names of clock correseponding IDs clock property as requested

	       by the controller driver.



Exynos5250:

- compatible : should be "samsung,exynos5250-usbphy"

- compatible : should be "samsung,exynos5250-usb2phy"

- reg : base physical address of the phy registers and length of memory mapped

	region.
@@ -44,12 +49,69 @@ Example: 
	usbphy@125B0000 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "samsung,exynos4210-usbphy";

		compatible = "samsung,exynos4210-usb2phy";

		reg = <0x125B0000 0x100>;

		ranges;



		clocks = <&clock 2>, <&clock 305>;

		clock-names = "xusbxti", "otg";



		usbphy-sys {

			/* USB device and host PHY_CONTROL registers */

			reg = <0x10020704 0x8>;

		};

	};





** Samsung's usb 3.0 phy transceiver



Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver

which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0

controllers across Samsung SOCs.



Required properties:



Exynos5250:

- compatible : should be "samsung,exynos5250-usb3phy"

- reg : base physical address of the phy registers and length of memory mapped

	region.

- clocks: Clock IDs array as required by the controller.

- clock-names: names of clocks correseponding to IDs in the clock property

	       as requested by the controller driver.



Optional properties:

- #address-cells: should be '1' when usbphy node has a child node with 'reg'

		  property.

- #size-cells: should be '1' when usbphy node has a child node with 'reg'

	       property.

- ranges: allows valid translation between child's address space and parent's

	  address space.



- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller

  interface for usb-phy. It should provide the following information required by

  usb-phy controller to control phy.

  - reg : base physical address of PHY_CONTROL registers.

	  The size of this register is the total sum of size of all PHY_CONTROL

	  registers that the SoC has. For example, the size will be

	  '0x4' in case we have only one PHY_CONTROL register (e.g.

	  OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)

	  and, '0x8' in case we have two PHY_CONTROL registers (e.g.

	  USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).

	  and so on.



Example:

	usbphy@12100000 {

		compatible = "samsung,exynos5250-usb3phy";

		reg = <0x12100000 0x100>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		clocks = <&clock 1>, <&clock 286>;

		clock-names = "ext_xtal", "usbdrd30";



		usbphy-sys {

			/* USB device and host PHY_CONTROL registers */

			reg = <0x10040704 0x8>;

		};

	};

Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt

0 → 100644
+34 −0
Original line number Diff line number Diff line 
USB NOP PHY



Required properties:

- compatible: should be usb-nop-xceiv



Optional properties:

- clocks: phandle to the PHY clock. Use as per Documentation/devicetree

  /bindings/clock/clock-bindings.txt

  This property is required if clock-frequency is specified.



- clock-names: Should be "main_clk"



- clock-frequency: the clock frequency (in Hz) that the PHY clock must

  be configured to.



- vcc-supply: phandle to the regulator that provides RESET to the PHY.



- reset-supply: phandle to the regulator that provides power to the PHY.



Example:



	hsusb1_phy {

		compatible = "usb-nop-xceiv";

		clock-frequency = <19200000>;

		clocks = <&osc 0>;

		clock-names = "main_clk";

		vcc-supply = <&hsusb1_vcc_regulator>;

		reset-supply = <&hsusb1_reset_regulator>;

	};



hsusb1_phy is a NOP USB PHY device that gets its clock from an oscillator

and expects that clock to be configured to 19.2MHz by the NOP PHY driver.

hsusb1_vcc_regulator provides power to the PHY and hsusb1_reset_regulator

controls RESET.

arch/arm/mach-mmp/aspenite.c

+0 −6
Original line number Diff line number Diff line
@@ -223,13 +223,7 @@ static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = { 
};



#if defined(CONFIG_USB_EHCI_MV)

static char *pxa168_sph_clock_name[] = {

	[0] = "PXA168-USBCLK",

};



static struct mv_usb_platform_data pxa168_sph_pdata = {

	.clknum         = 1,

	.clkname        = pxa168_sph_clock_name,

	.mode           = MV_USB_MODE_HOST,

	.phy_init	= pxa_usb_phy_init,

	.phy_deinit	= pxa_usb_phy_deinit,

arch/arm/mach-mmp/ttc_dkb.c

+0 −6
Original line number Diff line number Diff line
@@ -162,13 +162,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { 
#ifdef CONFIG_USB_SUPPORT

#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)



static char *pxa910_usb_clock_name[] = {

	[0] = "U2OCLK",

};



static struct mv_usb_platform_data ttc_usb_pdata = {

	.clknum		= 1,

	.clkname	= pxa910_usb_clock_name,

	.vbus		= NULL,

	.mode		= MV_USB_MODE_OTG,

	.otg_force_a_bus_req = 1,