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Commit 63e2074d authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Don't overwrite the VBIF XIN offset for A3xx 



Currently VBIF XIN register offset is been overwritten by
the AXI offset. This will cause VBIF XIN halt time out in
VBIF clear transaction path. Fix this by using the proper
VBIF XIN offset for A3xx targets.

Change-Id: Iac20528cb105904e46e012d67287dd736fa11f70
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 7568ce9a

drivers/gpu/msm/a3xx_reg.h

+2 −6
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -548,15 +548,11 @@ 


#define A3XX_VBIF_XIN_HALT_CTRL0 0x3080

#define A3XX_VBIF_XIN_HALT_CTRL0_MASK 0x3F

#define A30X_VBIF_XIN_HALT_CTRL0_MASK 0x7



#define A3XX_VBIF_XIN_HALT_CTRL1 0x3081



/* VBIF register offsets for A306 */

#define A3XX_VBIF2_XIN_HALT_CTRL0 0x3081

#define A3XX_VBIF2_XIN_HALT_CTRL0_MASK 0x7



#define A3XX_VBIF2_XIN_HALT_CTRL1 0x3082



#define A3XX_VBIF2_PERF_CNT_EN0 0x30c0

#define A3XX_VBIF2_PERF_CNT_EN1 0x30c1

#define A3XX_VBIF2_PERF_CNT_EN2 0x30c2

drivers/gpu/msm/adreno_a3xx.c

+4 −9
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -596,17 +596,12 @@ int adreno_a3xx_pwron_fixup_init(struct adreno_device *adreno_dev) 
static void a3xx_platform_setup(struct adreno_device *adreno_dev)

{

	struct adreno_gpudev *gpudev;

	const struct adreno_reg_offsets *reg_offsets;



	if (adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev)) {

	if (adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev)

			|| adreno_is_a304(adreno_dev)) {

		gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		reg_offsets = gpudev->reg_offsets;

		reg_offsets->offsets[ADRENO_REG_VBIF_XIN_HALT_CTRL0] =

			A3XX_VBIF2_XIN_HALT_CTRL0;

		reg_offsets->offsets[ADRENO_REG_VBIF_XIN_HALT_CTRL1] =

			A3XX_VBIF2_XIN_HALT_CTRL1;

		gpudev->vbif_xin_halt_ctrl0_mask =

				A3XX_VBIF2_XIN_HALT_CTRL0_MASK;

				A30X_VBIF_XIN_HALT_CTRL0_MASK;

	}

}