Loading sound/soc/codecs/tlv320aic26.c +11 −3 Original line number Original line Diff line number Diff line Loading @@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream, dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; } } /* Configure PLL */ /** * Configure PLL * fsref = (mclk * PLLM) / 2048 * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal) */ pval = 1; pval = 1; jval = (fsref == 44100) ? 7 : 8; /* compute J portion of multiplier */ dval = (fsref == 44100) ? 5264 : 1920; jval = fsref / (aic26->mclk / 2048); /* compute fractional DDDD component of multiplier */ dval = fsref - (jval * (aic26->mclk / 2048)); dval = (10000 * dval) / (aic26->mclk / 2048); dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval); qval = 0; qval = 0; reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg); aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg); Loading sound/soc/codecs/tlv320aic3x.c +8 −1 Original line number Original line Diff line number Diff line Loading @@ -1114,12 +1114,19 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power) /* Sync reg_cache with the hardware */ /* Sync reg_cache with the hardware */ codec->cache_only = 0; codec->cache_only = 0; for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) snd_soc_write(codec, i, cache[i]); snd_soc_write(codec, i, cache[i]); if (aic3x->model == AIC3X_MODEL_3007) if (aic3x->model == AIC3X_MODEL_3007) aic3x_init_3007(codec); aic3x_init_3007(codec); codec->cache_sync = 0; codec->cache_sync = 0; } else { } else { /* * Do soft reset to this codec instance in order to clear * possible VDD leakage currents in case the supply regulators * remain on */ snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); codec->cache_sync = 1; aic3x->power = 0; aic3x->power = 0; /* HW writes are needless when bias is off */ /* HW writes are needless when bias is off */ codec->cache_only = 1; codec->cache_only = 1; Loading Loading
sound/soc/codecs/tlv320aic26.c +11 −3 Original line number Original line Diff line number Diff line Loading @@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream, dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL; } } /* Configure PLL */ /** * Configure PLL * fsref = (mclk * PLLM) / 2048 * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal) */ pval = 1; pval = 1; jval = (fsref == 44100) ? 7 : 8; /* compute J portion of multiplier */ dval = (fsref == 44100) ? 5264 : 1920; jval = fsref / (aic26->mclk / 2048); /* compute fractional DDDD component of multiplier */ dval = fsref - (jval * (aic26->mclk / 2048)); dval = (10000 * dval) / (aic26->mclk / 2048); dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval); qval = 0; qval = 0; reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg); aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg); Loading
sound/soc/codecs/tlv320aic3x.c +8 −1 Original line number Original line Diff line number Diff line Loading @@ -1114,12 +1114,19 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power) /* Sync reg_cache with the hardware */ /* Sync reg_cache with the hardware */ codec->cache_only = 0; codec->cache_only = 0; for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) snd_soc_write(codec, i, cache[i]); snd_soc_write(codec, i, cache[i]); if (aic3x->model == AIC3X_MODEL_3007) if (aic3x->model == AIC3X_MODEL_3007) aic3x_init_3007(codec); aic3x_init_3007(codec); codec->cache_sync = 0; codec->cache_sync = 0; } else { } else { /* * Do soft reset to this codec instance in order to clear * possible VDD leakage currents in case the supply regulators * remain on */ snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); codec->cache_sync = 1; aic3x->power = 0; aic3x->power = 0; /* HW writes are needless when bias is off */ /* HW writes are needless when bias is off */ codec->cache_only = 1; codec->cache_only = 1; Loading