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Commit 63946615 authored by Archana Sathyakumar's avatar Archana Sathyakumar Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Support AVS_CTL register write for msmcobalt 



CPRh communicates voltages to the PMIC via L2 SAW4.
APCLUS{0,1}_L2_SAW4_AVS_CTL/LIMIT registers need to be programmed for
CPRh operation.

CRs-fixed: 987593
Change-Id: I635d710759a94e2bb29fd3c7811816d09243de50
Signed-off-by: default avatarArchana Sathyakumar <asathyak@codeaurora.org>
parent 0b20839e

arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -11,6 +11,38 @@ 
 */



&soc {

	qcom,spm@178120000 {

		compatible = "qcom,spm-v2";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x17812000 0x1000>;

		qcom,name = "gold-l2"; /* Gold L2 SAW */

		qcom,saw2-ver-reg = <0xfd0>;

		qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,vctl-timeout-us = <50>;

		qcom,vctl-port = <0x0>;

		qcom,phase-port = <0x1>;

		qcom,saw2-avs-ctl = <0x1010031>;

		qcom,saw2-avs-limit = <0x4000208>;

		qcom,pfm-port = <0x2>;

	};



	qcom,spm@179120000 {

		compatible = "qcom,spm-v2";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x17912000 0x1000>;

		qcom,name = "silver-l2"; /* Silver L2 SAW */

		qcom,saw2-ver-reg = <0xfd0>;

		qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,vctl-timeout-us = <50>;

		qcom,vctl-port = <0x0>;

		qcom,phase-port = <0x1>;

		qcom,saw2-avs-ctl = <0x1010031>;

		qcom,saw2-avs-limit = <0x4000208>;

		qcom,pfm-port = <0x2>;

	};



	qcom,lpm-levels {

		compatible = "qcom,lpm-levels";

		qcom,use-psci;