Loading arch/arm/boot/dts/qcom/msm8996.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -1207,8 +1207,8 @@ ufs_ice: ufsice@630000 { compatible = "qcom,ice"; reg = <0x630000 0x8000>; interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; interrupts = <0 258 0>, <0 257 0>; interrupt-names = "ufs_ice_nonsec_level_irq"; interrupts = <0 258 0>; qcom,enable-ice-clk; clock-names = "ufs_core_clk_src", "ufs_core_clk", Loading Loading @@ -1240,8 +1240,8 @@ sdcc1_ice: sdcc1ice@7443000 { compatible = "qcom,ice"; reg = <0x7443000 0x8000>; interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq"; interrupts = <0 461 0>, <0 460 0>; interrupt-names = "sdcc_ice_nonsec_level_irq"; interrupts = <0 461 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; Loading Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -1207,8 +1207,8 @@ ufs_ice: ufsice@630000 { compatible = "qcom,ice"; reg = <0x630000 0x8000>; interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; interrupts = <0 258 0>, <0 257 0>; interrupt-names = "ufs_ice_nonsec_level_irq"; interrupts = <0 258 0>; qcom,enable-ice-clk; clock-names = "ufs_core_clk_src", "ufs_core_clk", Loading Loading @@ -1240,8 +1240,8 @@ sdcc1_ice: sdcc1ice@7443000 { compatible = "qcom,ice"; reg = <0x7443000 0x8000>; interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq"; interrupts = <0 461 0>, <0 460 0>; interrupt-names = "sdcc_ice_nonsec_level_irq"; interrupts = <0 461 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; Loading