Loading drivers/net/8139cp.c +1 −1 Original line number Diff line number Diff line Loading @@ -598,8 +598,8 @@ rx_next: goto rx_status_loop; spin_lock_irqsave(&cp->lock, flags); cpw16_f(IntrMask, cp_intr_mask); __napi_complete(napi); cpw16_f(IntrMask, cp_intr_mask); spin_unlock_irqrestore(&cp->lock, flags); } Loading drivers/net/8139too.c +2 −1 Original line number Diff line number Diff line Loading @@ -860,6 +860,7 @@ retry: } /* if unknown chip, assume array element #0, original RTL-8139 in this case */ i = 0; dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); tp->chipset = 0; Loading Loading @@ -2088,8 +2089,8 @@ static int rtl8139_poll(struct napi_struct *napi, int budget) * again when we think we are done. */ spin_lock_irqsave(&tp->lock, flags); RTL_W16_F(IntrMask, rtl8139_intr_mask); __napi_complete(napi); RTL_W16_F(IntrMask, rtl8139_intr_mask); spin_unlock_irqrestore(&tp->lock, flags); } spin_unlock(&tp->rx_lock); Loading drivers/net/gianfar.c +1 −2 Original line number Diff line number Diff line Loading @@ -747,8 +747,7 @@ static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev) FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | FSL_GIANFAR_DEV_HAS_TIMER; FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; ctype = of_get_property(np, "phy-connection-type", NULL); Loading drivers/net/phy/lxt.c +50 −1 Original line number Diff line number Diff line Loading @@ -53,6 +53,9 @@ #define MII_LXT971_ISR 19 /* Interrupt Status Register */ /* register definitions for the 973 */ #define MII_LXT973_PCR 16 /* Port Configuration Register */ #define PCR_FIBER_SELECT 1 MODULE_DESCRIPTION("Intel LXT PHY driver"); MODULE_AUTHOR("Andy Fleming"); Loading Loading @@ -119,6 +122,33 @@ static int lxt971_config_intr(struct phy_device *phydev) return err; } static int lxt973_probe(struct phy_device *phydev) { int val = phy_read(phydev, MII_LXT973_PCR); if (val & PCR_FIBER_SELECT) { /* * If fiber is selected, then the only correct setting * is 100Mbps, full duplex, and auto negotiation off. */ val = phy_read(phydev, MII_BMCR); val |= (BMCR_SPEED100 | BMCR_FULLDPLX); val &= ~BMCR_ANENABLE; phy_write(phydev, MII_BMCR, val); /* Remember that the port is in fiber mode. */ phydev->priv = lxt973_probe; } else { phydev->priv = NULL; } return 0; } static int lxt973_config_aneg(struct phy_device *phydev) { /* Do nothing if port is in fiber mode. */ return phydev->priv ? 0 : genphy_config_aneg(phydev); } static struct phy_driver lxt970_driver = { .phy_id = 0x78100000, .name = "LXT970", Loading Loading @@ -146,6 +176,18 @@ static struct phy_driver lxt971_driver = { .driver = { .owner = THIS_MODULE,}, }; static struct phy_driver lxt973_driver = { .phy_id = 0x00137a10, .name = "LXT973", .phy_id_mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, .flags = 0, .probe = lxt973_probe, .config_aneg = lxt973_config_aneg, .read_status = genphy_read_status, .driver = { .owner = THIS_MODULE,}, }; static int __init lxt_init(void) { int ret; Loading @@ -157,8 +199,14 @@ static int __init lxt_init(void) ret = phy_driver_register(&lxt971_driver); if (ret) goto err2; ret = phy_driver_register(&lxt973_driver); if (ret) goto err3; return 0; err3: phy_driver_unregister(&lxt971_driver); err2: phy_driver_unregister(&lxt970_driver); err1: Loading @@ -169,6 +217,7 @@ static void __exit lxt_exit(void) { phy_driver_unregister(&lxt970_driver); phy_driver_unregister(&lxt971_driver); phy_driver_unregister(&lxt973_driver); } module_init(lxt_init); Loading drivers/net/r8169.c +9 −3 Original line number Diff line number Diff line Loading @@ -560,10 +560,10 @@ static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) udelay(25); } /* * Some configurations require a small delay even after the write * completed indication or the next write might fail. * According to hardware specs a 20us delay is required after write * complete indication, but before sending next command. */ udelay(25); udelay(20); } static int mdio_read(void __iomem *ioaddr, int reg_addr) Loading @@ -583,6 +583,12 @@ static int mdio_read(void __iomem *ioaddr, int reg_addr) } udelay(25); } /* * According to hardware specs a 20us delay is required after read * complete indication, but before sending next command. */ udelay(20); return value; } Loading Loading
drivers/net/8139cp.c +1 −1 Original line number Diff line number Diff line Loading @@ -598,8 +598,8 @@ rx_next: goto rx_status_loop; spin_lock_irqsave(&cp->lock, flags); cpw16_f(IntrMask, cp_intr_mask); __napi_complete(napi); cpw16_f(IntrMask, cp_intr_mask); spin_unlock_irqrestore(&cp->lock, flags); } Loading
drivers/net/8139too.c +2 −1 Original line number Diff line number Diff line Loading @@ -860,6 +860,7 @@ retry: } /* if unknown chip, assume array element #0, original RTL-8139 in this case */ i = 0; dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); tp->chipset = 0; Loading Loading @@ -2088,8 +2089,8 @@ static int rtl8139_poll(struct napi_struct *napi, int budget) * again when we think we are done. */ spin_lock_irqsave(&tp->lock, flags); RTL_W16_F(IntrMask, rtl8139_intr_mask); __napi_complete(napi); RTL_W16_F(IntrMask, rtl8139_intr_mask); spin_unlock_irqrestore(&tp->lock, flags); } spin_unlock(&tp->rx_lock); Loading
drivers/net/gianfar.c +1 −2 Original line number Diff line number Diff line Loading @@ -747,8 +747,7 @@ static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev) FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | FSL_GIANFAR_DEV_HAS_TIMER; FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; ctype = of_get_property(np, "phy-connection-type", NULL); Loading
drivers/net/phy/lxt.c +50 −1 Original line number Diff line number Diff line Loading @@ -53,6 +53,9 @@ #define MII_LXT971_ISR 19 /* Interrupt Status Register */ /* register definitions for the 973 */ #define MII_LXT973_PCR 16 /* Port Configuration Register */ #define PCR_FIBER_SELECT 1 MODULE_DESCRIPTION("Intel LXT PHY driver"); MODULE_AUTHOR("Andy Fleming"); Loading Loading @@ -119,6 +122,33 @@ static int lxt971_config_intr(struct phy_device *phydev) return err; } static int lxt973_probe(struct phy_device *phydev) { int val = phy_read(phydev, MII_LXT973_PCR); if (val & PCR_FIBER_SELECT) { /* * If fiber is selected, then the only correct setting * is 100Mbps, full duplex, and auto negotiation off. */ val = phy_read(phydev, MII_BMCR); val |= (BMCR_SPEED100 | BMCR_FULLDPLX); val &= ~BMCR_ANENABLE; phy_write(phydev, MII_BMCR, val); /* Remember that the port is in fiber mode. */ phydev->priv = lxt973_probe; } else { phydev->priv = NULL; } return 0; } static int lxt973_config_aneg(struct phy_device *phydev) { /* Do nothing if port is in fiber mode. */ return phydev->priv ? 0 : genphy_config_aneg(phydev); } static struct phy_driver lxt970_driver = { .phy_id = 0x78100000, .name = "LXT970", Loading Loading @@ -146,6 +176,18 @@ static struct phy_driver lxt971_driver = { .driver = { .owner = THIS_MODULE,}, }; static struct phy_driver lxt973_driver = { .phy_id = 0x00137a10, .name = "LXT973", .phy_id_mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, .flags = 0, .probe = lxt973_probe, .config_aneg = lxt973_config_aneg, .read_status = genphy_read_status, .driver = { .owner = THIS_MODULE,}, }; static int __init lxt_init(void) { int ret; Loading @@ -157,8 +199,14 @@ static int __init lxt_init(void) ret = phy_driver_register(&lxt971_driver); if (ret) goto err2; ret = phy_driver_register(&lxt973_driver); if (ret) goto err3; return 0; err3: phy_driver_unregister(&lxt971_driver); err2: phy_driver_unregister(&lxt970_driver); err1: Loading @@ -169,6 +217,7 @@ static void __exit lxt_exit(void) { phy_driver_unregister(&lxt970_driver); phy_driver_unregister(&lxt971_driver); phy_driver_unregister(&lxt973_driver); } module_init(lxt_init); Loading
drivers/net/r8169.c +9 −3 Original line number Diff line number Diff line Loading @@ -560,10 +560,10 @@ static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) udelay(25); } /* * Some configurations require a small delay even after the write * completed indication or the next write might fail. * According to hardware specs a 20us delay is required after write * complete indication, but before sending next command. */ udelay(25); udelay(20); } static int mdio_read(void __iomem *ioaddr, int reg_addr) Loading @@ -583,6 +583,12 @@ static int mdio_read(void __iomem *ioaddr, int reg_addr) } udelay(25); } /* * According to hardware specs a 20us delay is required after read * complete indication, but before sending next command. */ udelay(20); return value; } Loading