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Commit 61f3d0a9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull spi updates from Mark Brown:
 "A fairly quiet release for SPI, mainly driver work.  A few highlights:

   - Supports bits per word compatibility checking in the core.
   - Allow use of the IP used in Freescale SPI controllers outside
     Freescale SoCs.
   - DMA support for the Atmel SPI driver.
   - New drivers for the BCM2835 and Tegra114"

* tag 'spi-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (68 commits)
  spi-topcliff-pch: fix to use list_for_each_entry_safe() when delete list items
  spi-topcliff-pch: missing platform_driver_unregister() on error in pch_spi_init()
  ARM: dts: add pinctrl property for spi node for atmel SoC
  ARM: dts: add spi nodes for the atmel boards
  ARM: dts: add spi nodes for atmel SoC
  ARM: at91: add clocks for spi dt entries
  spi/spi-atmel: add dmaengine support
  spi/spi-atmel: add flag to controller data for lock operations
  spi/spi-atmel: add physical base address
  spi/sirf: fix MODULE_DEVICE_TABLE
  MAINTAINERS: Add git repository and update my address
  spi/s3c64xx: Check for errors in dmaengine prepare_transfer()
  spi/s3c64xx: Fix non-dmaengine usage
  spi: omap2-mcspi: fix error return code in omap2_mcspi_probe()
  spi/s3c64xx: let device core setup the default pin configuration
  MAINTAINERS: Update Grant's email address and maintainership
  spi: omap2-mcspi: Fix transfers if DMADEVICES is not set
  spi: s3c64xx: move to generic dmaengine API
  spi-gpio: init CS before spi_bitbang_setup()
  spi: spi-mpc512x-psc: let transmiter/receiver enabled when in xfer loop
  ...
parents 8ded8d4e cd8d984f
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Broadcom BCM2835 SPI0 controller

The BCM2835 contains two forms of SPI master controller, one known simply as
SPI0, and the other known as the "Universal SPI Master"; part of the
auxilliary block. This binding applies to the SPI0 controller.

Required properties:
- compatible: Should be "brcm,bcm2835-spi".
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: The clock feeding the SPI controller.

Example:

spi@20204000 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204000 0x1000>;
	interrupts = <2 22>;
	clocks = <&clk_spi>;
	#address-cells = <1>;
	#size-cells = <0>;
};
+2 −1
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@@ -4,7 +4,7 @@ Required properties:
- cell-index : QE SPI subblock index.
		0: QE subblock SPI1
		1: QE subblock SPI2
- compatible : should be "fsl,spi".
- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
@@ -14,6 +14,7 @@ Required properties:
  controller you have.
- interrupt-parent : the phandle for the interrupt controller that
  services interrupts for this device.
- clock-frequency : input clock frequency to non FSL_SOC cores

Optional properties:
- gpios : specifies the gpio pins to be used for chipselects.
+26 −0
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NVIDIA Tegra114 SPI controller.

Required properties:
- compatible : should be "nvidia,tegra114-spi".
- reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts.
- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
  request selector for this SPI controller.
- This is also require clock named "spi" as per binding document
  Documentation/devicetree/bindings/clock/clock-bindings.txt

Recommended properties:
- spi-max-frequency: Definition as per
                     Documentation/devicetree/bindings/spi/spi-bus.txt
Example:

spi@7000d600 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000d600 0x200>;
	interrupts = <0 82 0x04>;
	nvidia,dma-request-selector = <&apbdma 16>;
	spi-max-frequency = <25000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
};
+2 −6
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@@ -31,9 +31,6 @@ Required Board Specific Properties:

- #address-cells: should be 1.
- #size-cells: should be 0.
- gpios: The gpio specifier for clock, mosi and miso interface lines (in the
  order specified). The format of the gpio specifier depends on the gpio
  controller.

Optional Board Specific Properties:

@@ -86,9 +83,8 @@ Example:
	spi_0: spi@12d20000 {
		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&gpa2 4 2 3 0>,
			<&gpa2 6 2 3 0>,
			<&gpa2 7 2 3 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_bus>;

		w25q80bw@0 {
			#address-cells = <1>;
+1 −0
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@@ -5,6 +5,7 @@ using them to avoid name-space collisions.

ad	Avionic Design GmbH
adi	Analog Devices, Inc.
aeroflexgaisler	Aeroflex Gaisler AB
ak	Asahi Kasei Corp.
amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
apm	Applied Micro Circuits Corporation (APM)
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