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Commit 61d28b39 authored by Zhen Kong's avatar Zhen Kong
Browse files

ARM: dts: msm: correct CE clock setting for crypto driver on msm8996 



Correct CE clock setting for crypto drivers, core_clk_src should
link to voting clock; otherwise, ce1 clock is set to be only half
of 171M HZ during crypto operations.

Change-Id: I0d9e048381a83d4788bf4f700d788137b59bd368
Signed-off-by: default avatarZhen Kong <zkong@codeaurora.org>
parent 1b1ec93f

arch/arm/boot/dts/qcom/msm8996.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -2418,7 +2418,7 @@ 
				<55 512 3936000 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc clk_ce1_clk>,

		clocks = <&clock_gcc clk_qcrypto_ce1_clk>,

			 <&clock_gcc clk_qcrypto_ce1_clk>,

			 <&clock_gcc clk_gcc_ce1_ahb_m_clk>,

			 <&clock_gcc clk_gcc_ce1_axi_m_clk>;
@@ -2448,7 +2448,7 @@ 
				<55 512 3936000 393600>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		clocks = <&clock_gcc clk_ce1_clk>,

		clocks = <&clock_gcc clk_qcedev_ce1_clk>,

			 <&clock_gcc clk_qcedev_ce1_clk>,

			 <&clock_gcc clk_gcc_ce1_ahb_m_clk>,

			 <&clock_gcc clk_gcc_ce1_axi_m_clk>;