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Commit 619efb10 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
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drm/radeon/kms: Enable new pll calculation for avivo+ asics 

New algo is used for r5xx+ and legacy is used for
r1xx-r4xx, rv515.

I've tested on all relevant GPUs and monitors that I
have access to and have found no problems.

Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=26562
https://bugzilla.kernel.org/show_bug.cgi?id=26552
May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=32556



Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Cc: stable@kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f523f74e

drivers/gpu/drm/radeon/atombios_crtc.c

+16 −2
Original line number Diff line number Diff line
@@ -555,6 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
					dp_clock = dig_connector->dp_clock;

				}

			}

/* this might work properly with the new pll algo */

#if 0 /* doesn't work properly on some laptops */

			/* use recommended ref_div for ss */

			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
@@ -572,6 +573,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
					adjusted_clock = mode->clock * 2;

				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))

					pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;

				/* rv515 needs more testing with this option */

				if (rdev->family != CHIP_RV515) {

					if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))

						pll->flags |= RADEON_PLL_IS_LCD;

				}

			} else {

				if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)

					pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -951,6 +957,14 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
	/* adjust pixel clock as needed */

	adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);



	/* rv515 seems happier with the old algo */

	if (rdev->family == CHIP_RV515)

		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,

					  &ref_div, &post_div);

	else if (ASIC_IS_AVIVO(rdev))

		radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,

					 &ref_div, &post_div);

	else

		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,

					  &ref_div, &post_div);

drivers/gpu/drm/radeon/radeon_atombios.c

+0 −10
Original line number Diff line number Diff line
@@ -1163,16 +1163,6 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) 
				p1pll->pll_out_min = 64800;

			else

				p1pll->pll_out_min = 20000;

		} else if (p1pll->pll_out_min > 64800) {

			/* Limiting the pll output range is a good thing generally as

			 * it limits the number of possible pll combinations for a given

			 * frequency presumably to the ones that work best on each card.

			 * However, certain duallink DVI monitors seem to like

			 * pll combinations that would be limited by this at least on

			 * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per

			 * family.

			 */

			p1pll->pll_out_min = 64800;

		}



		p1pll->pll_in_min =

drivers/gpu/drm/radeon/radeon_display.c

+3 −0
Original line number Diff line number Diff line
@@ -935,6 +935,9 @@ void radeon_compute_pll_legacy(struct radeon_pll *pll, 
		pll_out_max = pll->pll_out_max;

	}



	if (pll_out_min > 64800)

		pll_out_min = 64800;



	if (pll->flags & RADEON_PLL_USE_REF_DIV)

		min_ref_div = max_ref_div = pll->reference_div;

	else {