Loading arch/x86/kernel/mpparse_32.c +21 −3 Original line number Diff line number Diff line Loading @@ -221,6 +221,8 @@ static void __init MP_bus_info (struct mpc_config_bus *m) } } #ifdef CONFIG_X86_IO_APIC static int bad_ioapic(unsigned long address) { if (nr_ioapics >= MAX_IO_APICS) { Loading Loading @@ -263,6 +265,8 @@ static void __init MP_intsrc_info (struct mpc_config_intsrc *m) panic("Max # of irq sources exceeded!!\n"); } #endif static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) { Dprintk("Lint: type %d, pol %d, trig %d, bus %d," Loading Loading @@ -421,21 +425,25 @@ static int __init smp_read_mpc(struct mp_config_table *mpc) } case MP_IOAPIC: { #ifdef CONFIG_X86_IO_APIC struct mpc_config_ioapic *m= (struct mpc_config_ioapic *)mpt; MP_ioapic_info(m); mpt+=sizeof(*m); count+=sizeof(*m); #endif break; } case MP_INTSRC: { #ifdef CONFIG_X86_IO_APIC struct mpc_config_intsrc *m= (struct mpc_config_intsrc *)mpt; MP_intsrc_info(m); mpt+=sizeof(*m); count+=sizeof(*m); #endif break; } case MP_LINTSRC: Loading Loading @@ -463,6 +471,8 @@ static int __init smp_read_mpc(struct mp_config_table *mpc) return num_processors; } #ifdef CONFIG_X86_IO_APIC static int __init ELCR_trigger(unsigned int irq) { unsigned int port; Loading Loading @@ -537,11 +547,15 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type) MP_intsrc_info(&intsrc); } #endif static inline void __init construct_default_ISA_mptable(int mpc_default_type) { struct mpc_config_processor processor; struct mpc_config_bus bus; #ifdef CONFIG_X86_IO_APIC struct mpc_config_ioapic ioapic; #endif struct mpc_config_lintsrc lintsrc; int linttypes[2] = { mp_ExtINT, mp_NMI }; int i; Loading Loading @@ -597,6 +611,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type) MP_bus_info(&bus); } #ifdef CONFIG_X86_IO_APIC ioapic.mpc_type = MP_IOAPIC; ioapic.mpc_apicid = 2; ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; Loading @@ -608,7 +623,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type) * We set up most of the low 16 IO-APIC pins according to MPS rules. */ construct_default_ioirq_mptable(mpc_default_type); #endif lintsrc.mpc_type = MP_LINTSRC; lintsrc.mpc_irqflag = 0; /* conforming */ lintsrc.mpc_srcbusid = 0; Loading Loading @@ -670,6 +685,8 @@ void __init get_smp_config (void) printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); return; } #ifdef CONFIG_X86_IO_APIC /* * If there are no explicit MP IRQ entries, then we are * broken. We set up most of the low 16 IO-APIC pins to Loading @@ -687,7 +704,7 @@ void __init get_smp_config (void) construct_default_ioirq_mptable(0); } #endif } else BUG(); Loading Loading @@ -967,8 +984,9 @@ void __init mp_config_acpi_legacy_irqs (void) intsrc.mpc_type = MP_INTSRC; intsrc.mpc_irqflag = 0; /* Conforming */ intsrc.mpc_srcbus = MP_ISA_BUS; #ifdef CONFIG_X86_IO_APIC intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; #endif /* * Use the default configuration for the IRQs 0-15. Unless * overridden by (MADT) interrupt source override entries. Loading include/asm-x86/mach-default/mach_apic.h +2 −0 Original line number Diff line number Diff line Loading @@ -69,8 +69,10 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) static inline void setup_apic_routing(void) { #ifdef CONFIG_X86_IO_APIC printk("Enabling APIC mode: %s. Using %d I/O APICs\n", "Flat", nr_ioapics); #endif } static inline int apicid_to_node(int logical_apicid) Loading include/asm-x86/mpspec.h +0 −3 Original line number Diff line number Diff line Loading @@ -36,9 +36,6 @@ extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES]; extern unsigned int boot_cpu_physical_apicid; extern int smp_found_config; extern int nr_ioapics; extern int mp_irq_entries; extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; extern int mpc_default_type; extern unsigned long mp_lapic_addr; Loading Loading
arch/x86/kernel/mpparse_32.c +21 −3 Original line number Diff line number Diff line Loading @@ -221,6 +221,8 @@ static void __init MP_bus_info (struct mpc_config_bus *m) } } #ifdef CONFIG_X86_IO_APIC static int bad_ioapic(unsigned long address) { if (nr_ioapics >= MAX_IO_APICS) { Loading Loading @@ -263,6 +265,8 @@ static void __init MP_intsrc_info (struct mpc_config_intsrc *m) panic("Max # of irq sources exceeded!!\n"); } #endif static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) { Dprintk("Lint: type %d, pol %d, trig %d, bus %d," Loading Loading @@ -421,21 +425,25 @@ static int __init smp_read_mpc(struct mp_config_table *mpc) } case MP_IOAPIC: { #ifdef CONFIG_X86_IO_APIC struct mpc_config_ioapic *m= (struct mpc_config_ioapic *)mpt; MP_ioapic_info(m); mpt+=sizeof(*m); count+=sizeof(*m); #endif break; } case MP_INTSRC: { #ifdef CONFIG_X86_IO_APIC struct mpc_config_intsrc *m= (struct mpc_config_intsrc *)mpt; MP_intsrc_info(m); mpt+=sizeof(*m); count+=sizeof(*m); #endif break; } case MP_LINTSRC: Loading Loading @@ -463,6 +471,8 @@ static int __init smp_read_mpc(struct mp_config_table *mpc) return num_processors; } #ifdef CONFIG_X86_IO_APIC static int __init ELCR_trigger(unsigned int irq) { unsigned int port; Loading Loading @@ -537,11 +547,15 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type) MP_intsrc_info(&intsrc); } #endif static inline void __init construct_default_ISA_mptable(int mpc_default_type) { struct mpc_config_processor processor; struct mpc_config_bus bus; #ifdef CONFIG_X86_IO_APIC struct mpc_config_ioapic ioapic; #endif struct mpc_config_lintsrc lintsrc; int linttypes[2] = { mp_ExtINT, mp_NMI }; int i; Loading Loading @@ -597,6 +611,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type) MP_bus_info(&bus); } #ifdef CONFIG_X86_IO_APIC ioapic.mpc_type = MP_IOAPIC; ioapic.mpc_apicid = 2; ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; Loading @@ -608,7 +623,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type) * We set up most of the low 16 IO-APIC pins according to MPS rules. */ construct_default_ioirq_mptable(mpc_default_type); #endif lintsrc.mpc_type = MP_LINTSRC; lintsrc.mpc_irqflag = 0; /* conforming */ lintsrc.mpc_srcbusid = 0; Loading Loading @@ -670,6 +685,8 @@ void __init get_smp_config (void) printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); return; } #ifdef CONFIG_X86_IO_APIC /* * If there are no explicit MP IRQ entries, then we are * broken. We set up most of the low 16 IO-APIC pins to Loading @@ -687,7 +704,7 @@ void __init get_smp_config (void) construct_default_ioirq_mptable(0); } #endif } else BUG(); Loading Loading @@ -967,8 +984,9 @@ void __init mp_config_acpi_legacy_irqs (void) intsrc.mpc_type = MP_INTSRC; intsrc.mpc_irqflag = 0; /* Conforming */ intsrc.mpc_srcbus = MP_ISA_BUS; #ifdef CONFIG_X86_IO_APIC intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; #endif /* * Use the default configuration for the IRQs 0-15. Unless * overridden by (MADT) interrupt source override entries. Loading
include/asm-x86/mach-default/mach_apic.h +2 −0 Original line number Diff line number Diff line Loading @@ -69,8 +69,10 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) static inline void setup_apic_routing(void) { #ifdef CONFIG_X86_IO_APIC printk("Enabling APIC mode: %s. Using %d I/O APICs\n", "Flat", nr_ioapics); #endif } static inline int apicid_to_node(int logical_apicid) Loading
include/asm-x86/mpspec.h +0 −3 Original line number Diff line number Diff line Loading @@ -36,9 +36,6 @@ extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES]; extern unsigned int boot_cpu_physical_apicid; extern int smp_found_config; extern int nr_ioapics; extern int mp_irq_entries; extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; extern int mpc_default_type; extern unsigned long mp_lapic_addr; Loading