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Commit 60dbd768 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

ARM: sirf: move irq driver to drivers/irqchip 



This updates the irqchip drier for prima2 to the current practices by
moving it into drivers/irqchip and integrating it into the irqchip_init
infrastructure. We also now use a linear irq domain as a preparation
for sparse IRQ suport.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
parent 67d71344

arch/arm/mach-prima2/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -4,7 +4,6 @@ obj-y += rtciobrg.o 
obj-$(CONFIG_DEBUG_LL) += lluart.o

obj-$(CONFIG_CACHE_L2X0) += l2x0.o

obj-$(CONFIG_SUSPEND) += pm.o sleep.o

obj-$(CONFIG_SIRF_IRQ) += irq.o

obj-$(CONFIG_SMP) += platsmp.o headsmp.o

obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o

obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o

arch/arm/mach-prima2/common.c

+2 −8
Original line number Diff line number Diff line
@@ -46,11 +46,8 @@ static const char *atlas6_dt_match[] __initdata = { 
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")

	/* Maintainer: Barry Song <baohua.song@csr.com> */

	.map_io         = sirfsoc_map_io,

	.init_irq	= sirfsoc_of_irq_init,

	.init_irq	= irqchip_init,

	.init_time	= sirfsoc_prima2_timer_init,

#ifdef CONFIG_MULTI_IRQ_HANDLER

	.handle_irq     = sirfsoc_handle_irq,

#endif

	.init_machine	= sirfsoc_mach_init,

	.init_late	= sirfsoc_init_late,

	.dt_compat      = atlas6_dt_match,
@@ -67,11 +64,8 @@ static const char *prima2_dt_match[] __initdata = { 
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")

	/* Maintainer: Barry Song <baohua.song@csr.com> */

	.map_io         = sirfsoc_map_io,

	.init_irq	= sirfsoc_of_irq_init,

	.init_irq	= irqchip_init,

	.init_time	= sirfsoc_prima2_timer_init,

#ifdef CONFIG_MULTI_IRQ_HANDLER

	.handle_irq     = sirfsoc_handle_irq,

#endif

	.dma_zone_size	= SZ_256M,

	.init_machine	= sirfsoc_mach_init,

	.init_late	= sirfsoc_init_late,

drivers/irqchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o 
obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o

obj-$(CONFIG_ARM_GIC)			+= irq-gic.o

obj-$(CONFIG_ARM_VIC)			+= irq-vic.o

obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o

obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o

arch/arm/mach-prima2/irq.c→drivers/irqchip/irq-sirfsoc.c

+126 −0
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include <linux/syscore_ops.h>

#include <asm/mach/irq.h>

#include <asm/exception.h>

#include <mach/hardware.h>

#include "irqchip.h"



#define SIRFSOC_INT_RISC_MASK0          0x0018

#define SIRFSOC_INT_RISC_MASK1          0x001C
@@ -23,7 +23,9 @@ 
#define SIRFSOC_INT_RISC_LEVEL1         0x0024

#define SIRFSOC_INIT_IRQ_ID		0x0038



void __iomem *sirfsoc_intc_base;

#define SIRFSOC_NUM_IRQS		128



static struct irq_domain *sirfsoc_irqdomain;



static __init void

sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
@@ -41,53 +43,41 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) 
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);

}



static __init void sirfsoc_irq_init(void)

{

	sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);

	sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,

			SIRFSOC_INTENAL_IRQ_END + 1 - 32);



	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);

	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);



	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);

	writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);

}



asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)

static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)

{

	void __iomem *base = sirfsoc_irqdomain->host_data;

	u32 irqstat, irqnr;



	irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);

	irqnr = irqstat & 0xff;

	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);

	irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff);



	handle_IRQ(irqnr, regs);

}



static struct of_device_id intc_ids[]  = {

	{ .compatible = "sirf,prima2-intc" },

	{},

};



void __init sirfsoc_of_irq_init(void)

static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent)

{

	struct device_node *np;

	void __iomem *base = of_iomap(np, 0);

	if (!base)

		panic("unable to map intc cpu registers\n");



	np = of_find_matching_node(NULL, intc_ids);

	if (!np)

		return;

	/* using legacy because irqchip_generic does not work with linear */

	sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0,

				 &irq_domain_simple_ops, base);



	sirfsoc_intc_base = of_iomap(np, 0);

	if (!sirfsoc_intc_base)

		panic("unable to map intc cpu registers\n");

	sirfsoc_alloc_gc(base, 0, 32);

	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);



	irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,

		&irq_domain_simple_ops, NULL);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);



	of_node_put(np);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);



	sirfsoc_irq_init();

	set_handle_irq(sirfsoc_handle_irq);



	return 0;

}

IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);



struct sirfsoc_irq_status {

	u32 mask0;
@@ -100,20 +90,24 @@ static struct sirfsoc_irq_status sirfsoc_irq_st; 


static int sirfsoc_irq_suspend(void)

{

	sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);

	sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);

	sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);

	sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);

	void __iomem *base = sirfsoc_irqdomain->host_data;



	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);

	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);

	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);

	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);



	return 0;

}



static void sirfsoc_irq_resume(void)

{

	writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);

	writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);

	writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);

	writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);

	void __iomem *base = sirfsoc_irqdomain->host_data;



	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);

	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);

	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);

	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);

}



static struct syscore_ops sirfsoc_irq_syscore_ops = {
@@ -123,6 +117,9 @@ static struct syscore_ops sirfsoc_irq_syscore_ops = { 


static int __init sirfsoc_irq_pm_init(void)

{

	if (!sirfsoc_irqdomain)

		return 0;



	register_syscore_ops(&sirfsoc_irq_syscore_ops);

	return 0;

}