Merge "clk: msm: clock-mmss-cobalt: Add support for some display clocks" (60da1940) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-mmss-cobalt.c

+28 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1747,6 +1747,18 @@ static struct branch_clk mmss_mdss_byte0_clk = {
	},		},
	};		};

			static struct branch_clk mmss_mdss_byte0_intf_clk = {
			.cbcr_reg = MMSS_MDSS_BYTE0_INTF_CBCR,
			.has_sibling = 1,
			.base = &virt_base,
			.c = {
			.dbg_name = "mmss_mdss_byte0_intf_clk",
			.parent = &byte0_clk_src.c,
			.ops = &clk_ops_branch,
			CLK_INIT(mmss_mdss_byte0_intf_clk.c),
			},
			};

	static struct branch_clk mmss_mdss_byte1_clk = {		static struct branch_clk mmss_mdss_byte1_clk = {
	.cbcr_reg = MMSS_MDSS_BYTE1_CBCR,		.cbcr_reg = MMSS_MDSS_BYTE1_CBCR,
	.has_sibling = 0,		.has_sibling = 0,
	@@ -1759,6 +1771,18 @@ static struct branch_clk mmss_mdss_byte1_clk = {
	},		},
	};		};

			static struct branch_clk mmss_mdss_byte1_intf_clk = {
			.cbcr_reg = MMSS_MDSS_BYTE1_INTF_CBCR,
			.has_sibling = 1,
			.base = &virt_base,
			.c = {
			.dbg_name = "mmss_mdss_byte1_intf_clk",
			.parent = &byte1_clk_src.c,
			.ops = &clk_ops_branch,
			CLK_INIT(mmss_mdss_byte1_intf_clk.c),
			},
			};

	static struct branch_clk mmss_mdss_dp_aux_clk = {		static struct branch_clk mmss_mdss_dp_aux_clk = {
	.cbcr_reg = MMSS_MDSS_DP_AUX_CBCR,		.cbcr_reg = MMSS_MDSS_DP_AUX_CBCR,
	.has_sibling = 0,		.has_sibling = 0,
	@@ -2245,6 +2269,8 @@ static struct mux_clk mmss_debug_mux = {
	{ &mmss_throttle_camss_axi_clk.c, 0x00aa },		{ &mmss_throttle_camss_axi_clk.c, 0x00aa },
	{ &mmss_throttle_mdss_axi_clk.c, 0x00ab },		{ &mmss_throttle_mdss_axi_clk.c, 0x00ab },
	{ &mmss_throttle_video_axi_clk.c, 0x00ac },		{ &mmss_throttle_video_axi_clk.c, 0x00ac },
			{ &mmss_mdss_byte0_intf_clk.c, 0x00ad },
			{ &mmss_mdss_byte1_intf_clk.c, 0x00ae },
	),		),
	.c = {		.c = {
	.dbg_name = "mmss_debug_mux",		.dbg_name = "mmss_debug_mux",
	@@ -2381,7 +2407,9 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = {
	CLK_LIST(mmss_mdss_ahb_clk),		CLK_LIST(mmss_mdss_ahb_clk),
	CLK_LIST(mmss_mdss_axi_clk),		CLK_LIST(mmss_mdss_axi_clk),
	CLK_LIST(mmss_mdss_byte0_clk),		CLK_LIST(mmss_mdss_byte0_clk),
			CLK_LIST(mmss_mdss_byte0_intf_clk),
	CLK_LIST(mmss_mdss_byte1_clk),		CLK_LIST(mmss_mdss_byte1_clk),
			CLK_LIST(mmss_mdss_byte1_intf_clk),
	CLK_LIST(mmss_mdss_dp_aux_clk),		CLK_LIST(mmss_mdss_dp_aux_clk),
	CLK_LIST(mmss_mdss_dp_gtc_clk),		CLK_LIST(mmss_mdss_dp_gtc_clk),
	CLK_LIST(mmss_mdss_esc0_clk),		CLK_LIST(mmss_mdss_esc0_clk),

include/dt-bindings/clock/msm-clocks-cobalt.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -397,7 +397,9 @@
	#define clk_mmss_mdss_ahb_clk 0x85d37ab5		#define clk_mmss_mdss_ahb_clk 0x85d37ab5
	#define clk_mmss_mdss_axi_clk 0xdf04fc1d		#define clk_mmss_mdss_axi_clk 0xdf04fc1d
	#define clk_mmss_mdss_byte0_clk 0x38105d25		#define clk_mmss_mdss_byte0_clk 0x38105d25
			#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79
	#define clk_mmss_mdss_byte1_clk 0xe0c21354		#define clk_mmss_mdss_byte1_clk 0xe0c21354
			#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e
	#define clk_mmss_mdss_dp_aux_clk 0x23125eb6		#define clk_mmss_mdss_dp_aux_clk 0x23125eb6
	#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a		#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a
	#define clk_mmss_mdss_esc0_clk 0x5721ff83		#define clk_mmss_mdss_esc0_clk 0x5721ff83