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Commit 60751001 authored by Gabor Juhos's avatar Gabor Juhos Committed by John W. Linville
Browse files

rt2x00: rt2800lib: fix band selection and LNA PE control for RT3593 PCIe cards 



The band selection and PE control code for the
RT3593 chipsets only handles USB based devices
currently. Due to this limitation RT3593 based
PCIe cards are not working correctly.

On PCIe cards band selection is controlled via
GPIO #8 which is identical to the USB devices.
The LNA PE control is slightly different, all
LNA PEs are controlled by GPIO #4.

Update the code to configure the GPIO_CTRL register
correctly on PCIe devices.

Cc: Steven Liu <steven.liu@mediatek.com>
Cc: JasonYS Cheng <jasonys.cheng@mediatek.com>
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3001f0d0

drivers/net/wireless/rt2x00/rt2800lib.c

+17 −9
Original line number Original line Diff line number Diff line
@@ -3315,28 +3315,36 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 
		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);

		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);





	if (rt2x00_rt(rt2x00dev, RT3593)) {

	if (rt2x00_rt(rt2x00dev, RT3593)) {

		if (rt2x00_is_usb(rt2x00dev)) {

		rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);

		rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);





			/* Band selection. GPIO #8 controls all paths */

		/* Band selection */

		if (rt2x00_is_usb(rt2x00dev) ||

		    rt2x00_is_pcie(rt2x00dev)) {

			/* GPIO #8 controls all paths */

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);

			if (rf->channel <= 14)

			if (rf->channel <= 14)

				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);

				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);

			else

			else

				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);

				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);

		}





		/* LNA PE control. */

		if (rt2x00_is_usb(rt2x00dev)) {

			/* GPIO #4 controls PE0 and PE1,

			 * GPIO #7 controls PE2

			 */

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);





			/* LNA PE control.

			* GPIO #4 controls PE0 and PE1,

			* GPIO #7 controls PE2

			*/

			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);

			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);

			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);

			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);

		} else if (rt2x00_is_pcie(rt2x00dev)) {

			/* GPIO #4 controls PE0, PE1 and PE2 */

			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);

			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);

		}





		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);

		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);

		}





		/* AGC init */

		/* AGC init */

		if (rf->channel <= 14)

		if (rf->channel <= 14)