Merge "ARM: dts: msm: Add UFS and UFS PHY nodes for msmcobalt"

Required properties:

- compatible        : compatible list, contains "qcom,ufs-phy-qmp-20nm"

		      or "qcom,ufs-phy-qmp-14nm" according to the relevant

		      phy in use.

		      or "qcom,ufs-phy-qmp-14nm" or "qcom,ufs-phy-qmp-v3"

		      according to the relevant phy in use.

- reg               : should contain PHY register address space (mandatory),

- reg-names         : indicates various resources passed to driver (via reg proptery) by name.

                      Required "reg-names" is "phy_mem".

					<&glink_dsps>;

		qcom,xprt = "smem";

	};

	ufsphy1: ufsphy@1da7000 {

		compatible = "qcom,ufs-phy-qmp-v3";

		reg = <0x1da7000 0xda8>;

		reg-names = "phy_mem";

		#phy-cells = <0>;

		vdda-phy-max-microamp = <51430>;

		vdda-pll-max-microamp = <14170>;

		vddp-ref-clk-max-microamp = <100>;

		vddp-ref-clk-always-on;

		clock-names = "ref_clk_src",

			"ref_clk";

		clocks = <&clock_gcc clk_ln_bb_clk>,

			<&clock_gcc clk_gcc_ufs_clkref_clk>;

		status = "disabled";

	};

	ufs1: ufshc@1da4000 {

		compatible = "jedec,ufs-1.1";

		reg = <0x1da4000 0x2500>;

		interrupts = <0 265 0>;

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

		vdd-hba-fixed-regulator;

		vcc-max-microamp = <750000>;

		vccq-max-microamp = <450000>;

		vccq2-max-microamp = <750000>;

		clock-names =

			"core_clk_src",

			"core_clk",

			"iface_clk",

			"core_clk_unipro_src",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk";

		clocks =

			<&clock_gcc clk_ufs_axi_clk_src>,

			<&clock_gcc clk_gcc_ufs_axi_clk>,

			<&clock_gcc clk_gcc_ufs_ahb_clk>,

			<&clock_gcc clk_ufs_ice_core_clk_src>,

			<&clock_gcc clk_gcc_ufs_unipro_core_clk>,

			<&clock_gcc clk_gcc_ufs_ice_core_clk>,

			<&clock_gcc clk_bb_clk1>,

			<&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,

			<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;

		freq-table-hz =

			<100000000 200000000>,

			<0 0>,

			<0 0>,

			<150000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;

		lanes-per-direction = <1>;

		qcom,msm-bus,name = "ufs1";

		qcom,msm-bus,num-cases = <12>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		<95 512 0 0>, <1 650 0 0>,          /* No vote */

		<95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */

		<95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */

		<95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */

		<95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */

		<95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */

		<95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */

		<95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */

		<95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */

		<95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */

		<95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */

		<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"MAX";

		qcom,cpu-affinity = "affine_cores";

		qcom,cpu-dma-latency-us = <301>;

		status = "disabled";

		ufs_variant {

			compatible = "qcom,ufs_variant";

		};

	};

};

	  This select the type of UFS PHY to be used.

	  It must match the actual hardware found on your platform.

	config PHY_QCOM_UFS_V3

	bool "UFS QCOM v3 PHY"

	help

	  Select this if your platform has a v3 UFS PHY.

	config PHY_QCOM_UFS_14NM

	bool "UFS QCOM 14nm PHY"

	help

phy_qcom_ufs_mod-y				+= phy-qcom-ufs.o

phy_qcom_ufs_mod-$(CONFIG_PHY_QCOM_UFS_20NM)	+= phy-qcom-ufs-qmp-20nm.o

phy_qcom_ufs_mod-$(CONFIG_PHY_QCOM_UFS_14NM)	+= phy-qcom-ufs-qmp-14nm.o

phy_qcom_ufs_mod-$(CONFIG_PHY_QCOM_UFS_V3)	+= phy-qcom-ufs-qmp-v3.o

obj-$(CONFIG_PHY_QCOM_UFS)			+= phy_qcom_ufs_mod.o

obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)	+= phy-spear1310-miphy.o

obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)	+= phy-spear1340-miphy.o

/*

 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#include "phy-qcom-ufs-qmp-v3.h"

#define UFS_PHY_NAME "ufs_phy_qmp_v3"

static

int ufs_qcom_phy_qmp_v3_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

{

	int err;

	int tbl_size_A, tbl_size_B;

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;

	tbl_A = phy_cal_table_rate_A;

	tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);

	err = ufs_qcom_phy_calibrate(ufs_qcom_phy,

				     tbl_A, tbl_size_A,

				     tbl_B, tbl_size_B,

				     is_rate_B);

	if (err)

		dev_err(ufs_qcom_phy->dev,

			"%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);

	return err;

}

static int ufs_qcom_phy_qmp_v3_init(struct phy *generic_phy)

{

	struct ufs_qcom_phy_qmp_v3 *phy = phy_get_drvdata(generic_phy);

	struct ufs_qcom_phy *phy_common = &phy->common_cfg;

	int err;

	err = ufs_qcom_phy_init_clks(generic_phy, phy_common);

	if (err) {

		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",

			__func__, err);

		goto out;

	}

	err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);

	if (err) {

		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",

			__func__, err);

		goto out;

	}

out:

	return err;

}

static

void ufs_qcom_phy_qmp_v3_power_control(struct ufs_qcom_phy *phy,

					 bool power_ctrl)

{

	if (!power_ctrl) {

		/* apply analog power collapse */

		writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

		/*

		 * Make sure that PHY knows its analog rail is going to be

		 * powered OFF.

		 */

		mb();

	} else {

		/* bring PHY out of analog power collapse */

		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

		/*

		 * Before any transactions involving PHY, ensure PHY knows

		 * that it's analog rail is powered ON.

		 */

		mb();

	}

}

static inline

void ufs_qcom_phy_qmp_v3_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)

{

	/*

	 * v3 PHY does not have TX_LANE_ENABLE register.

	 * Implement this function so as not to propagate error to caller.

	 */

}

static

void ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)

{

	u32 temp;

	temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);

	if (ctrl) /* enable RX LineCfg */

		temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;

	else /* disable RX LineCfg */

		temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;

	writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);

	/* make sure that RX LineCfg config applied before we return */

	mb();

}

static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy)

{

	u32 tmp;

	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);

	tmp &= ~MASK_SERDES_START;

	tmp |= (1 << OFFSET_SERDES_START);

	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);

	/* Ensure register value is committed */

	mb();

}

static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common)

{

	int err = 0;

	u32 val;

	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,

		val, (val & MASK_PCS_READY), 10, 1000000);

	if (err) {

		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",

			__func__, err);

		goto out;

	}

out:

	return err;

}

struct phy_ops ufs_qcom_phy_qmp_v3_phy_ops = {

	.init		= ufs_qcom_phy_qmp_v3_init,

	.exit		= ufs_qcom_phy_exit,

	.power_on	= ufs_qcom_phy_power_on,

	.power_off	= ufs_qcom_phy_power_off,

	.owner		= THIS_MODULE,

};

struct ufs_qcom_phy_specific_ops phy_v3_ops = {

	.calibrate_phy		= ufs_qcom_phy_qmp_v3_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qmp_v3_start_serdes,

	.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v3_is_pcs_ready,

	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_set_tx_lane_enable,

	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg,

	.power_control		= ufs_qcom_phy_qmp_v3_power_control,

};

static int ufs_qcom_phy_qmp_v3_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy;

	struct ufs_qcom_phy_qmp_v3 *phy;

	int err = 0;

	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);

	if (!phy) {

		err = -ENOMEM;

		goto out;

	}

	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,

				&ufs_qcom_phy_qmp_v3_phy_ops, &phy_v3_ops);

	if (!generic_phy) {

		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",

			__func__);

		err = -EIO;

		goto out;

	}

	phy_set_drvdata(generic_phy, phy);

	strlcpy(phy->common_cfg.name, UFS_PHY_NAME,

		sizeof(phy->common_cfg.name));

out:

	return err;

}

static int ufs_qcom_phy_qmp_v3_remove(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy = to_phy(dev);

	struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);

	int err = 0;

	err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);

	if (err)

		dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",

			__func__, err);

	return err;

}

static const struct of_device_id ufs_qcom_phy_qmp_v3_of_match[] = {

	{.compatible = "qcom,ufs-phy-qmp-v3"},

	{},

};

MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_of_match);

static struct platform_driver ufs_qcom_phy_qmp_v3_driver = {

	.probe = ufs_qcom_phy_qmp_v3_probe,

	.remove = ufs_qcom_phy_qmp_v3_remove,

	.driver = {

		.of_match_table = ufs_qcom_phy_qmp_v3_of_match,

		.name = "ufs_qcom_phy_qmp_v3",

		.owner = THIS_MODULE,

	},

};

module_platform_driver(ufs_qcom_phy_qmp_v3_driver);

MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3");

MODULE_LICENSE("GPL v2");