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Commit 6023adcc authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: kgsl: use of_find_node_by_name() instead of rolling our own"

parents 4b6f02af b42e2119

drivers/gpu/msm/adreno.c

+5 −18
Original line number Diff line number Diff line
@@ -756,26 +756,13 @@ static const struct of_device_id adreno_match_table[] = { 
	{}

};



static struct device_node *adreno_of_find_subnode(struct device_node *parent,

	const char *name)

{

	struct device_node *child;



	for_each_child_of_node(parent, child) {

		if (of_device_is_compatible(child, name))

			return child;

	}



	return NULL;

}



static int adreno_of_get_pwrlevels(struct device_node *parent,

	struct kgsl_device_platform_data *pdata)

{

	struct device_node *node, *child;

	int ret = -EINVAL;



	node = adreno_of_find_subnode(parent, "qcom,gpu-pwrlevels");

	node = of_find_node_by_name(parent, "qcom,gpu-pwrlevels");



	if (node == NULL) {

		KGSL_CORE_ERR("Unable to find 'qcom,gpu-pwrlevels'\n");
@@ -1387,6 +1374,10 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	/* Set the bit to indicate that we've just powered on */

	set_bit(ADRENO_DEVICE_PWRON, &adreno_dev->priv);



	/* Soft reset the GPU if a regulator is stuck on*/

	if (regulator_left_on)

		_soft_reset(adreno_dev);



	status = kgsl_mmu_start(device);

	if (status)

		goto error_pwr_off;
@@ -1412,10 +1403,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
		goto error_mmu_off;

	}



	/* Soft reset GPU if regulator is stuck on*/

	if (regulator_left_on)

		_soft_reset(adreno_dev);



	if (adreno_dev->perfctr_pwr_lo == 0) {

		int ret = adreno_perfcounter_get(adreno_dev,

			KGSL_PERFCOUNTER_GROUP_PWR, 1,

drivers/gpu/msm/adreno.h

+25 −64
Original line number Diff line number Diff line
@@ -839,51 +839,26 @@ long adreno_ioctl_perfcounter_get(struct kgsl_device_private *dev_priv, 
long adreno_ioctl_perfcounter_put(struct kgsl_device_private *dev_priv,

	unsigned int cmd, void *data);



#define ADRENO_TARGET(_name, _id) \

static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \

{ \

	return (ADRENO_GPUREV(adreno_dev) == (_id)); \

}



static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)

{

	return ((ADRENO_GPUREV(adreno_dev) >= 300) &&

		(ADRENO_GPUREV(adreno_dev) < 400));

}



static inline int adreno_is_a304(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A304);

}



static inline int adreno_is_a305(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A305);

}



static inline int adreno_is_a305b(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A305B);

}



static inline int adreno_is_a305c(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A305C);

}



static inline int adreno_is_a306(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A306);

}



static inline int adreno_is_a310(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A310);

}



static inline int adreno_is_a320(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A320);

}



static inline int adreno_is_a330(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330);

}

ADRENO_TARGET(a304, ADRENO_REV_A304)

ADRENO_TARGET(a305, ADRENO_REV_A305)

ADRENO_TARGET(a305b, ADRENO_REV_A305B)

ADRENO_TARGET(a305c, ADRENO_REV_A305C)

ADRENO_TARGET(a306, ADRENO_REV_A306)

ADRENO_TARGET(a310, ADRENO_REV_A310)

ADRENO_TARGET(a320, ADRENO_REV_A320)

ADRENO_TARGET(a330, ADRENO_REV_A330)



static inline int adreno_is_a330v2(struct adreno_device *adreno_dev)

{
@@ -903,10 +878,7 @@ static inline int adreno_is_a4xx(struct adreno_device *adreno_dev) 
		ADRENO_GPUREV(adreno_dev) < 500;

}



static inline int adreno_is_a405(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A405);

}

ADRENO_TARGET(a405, ADRENO_REV_A405);



static inline int adreno_is_a405v2(struct adreno_device *adreno_dev)

{
@@ -914,25 +886,15 @@ static inline int adreno_is_a405v2(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0x10);

}



static inline int adreno_is_a420(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A420);

}



static inline int adreno_is_a430(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A430);

}

ADRENO_TARGET(a418, ADRENO_REV_A418)

ADRENO_TARGET(a420, ADRENO_REV_A420)

ADRENO_TARGET(a430, ADRENO_REV_A430)



static inline int adreno_is_a430v2(struct adreno_device *adreno_dev)

{

	return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A430) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 1));

}

static inline int adreno_is_a418(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A418);

}



static inline int adreno_is_a5xx(struct adreno_device *adreno_dev)

{
@@ -940,10 +902,8 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) 
			ADRENO_GPUREV(adreno_dev) < 600;

}



static inline int adreno_is_a530(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530;

}

ADRENO_TARGET(a510, ADRENO_REV_A510)

ADRENO_TARGET(a530, ADRENO_REV_A530)



static inline int adreno_is_a530v1(struct adreno_device *adreno_dev)

{
@@ -951,9 +911,10 @@ static inline int adreno_is_a530v1(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a510(struct adreno_device *adreno_dev)

static inline int adreno_is_a530v2(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A510;

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) != 0);

}



/**
@@ -1148,8 +1109,8 @@ static inline void adreno_vbif_start(struct adreno_device *adreno_dev, 
			break;

		}

	}

	BUG_ON(vbif == NULL);

	while (vbif->reg != 0) {



	while ((vbif != NULL) && (vbif->reg != 0)) {

		kgsl_regwrite(&adreno_dev->dev, vbif->reg, vbif->val);

		vbif++;

	}

drivers/gpu/msm/adreno_a5xx.c

+29 −13
Original line number Diff line number Diff line
@@ -944,13 +944,34 @@ static const struct kgsl_hwcg_reg a530_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static void a5xx_hwcg_init(struct kgsl_device *device,

	const struct kgsl_hwcg_reg *regs, unsigned int nregs)

static const struct {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct kgsl_hwcg_reg *regs;

	unsigned int count;

} a5xx_hwcg_registers[] = {

	{ adreno_is_a530v2, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

};



static void a5xx_hwcg_init(struct adreno_device *adreno_dev)

{

	unsigned int i;

	/* program revision specific HWCG settings */

	for (i = 0; i < nregs; i++)

		kgsl_regwrite(device, regs[i].off, regs[i].val);

	struct kgsl_device *device = &adreno_dev->dev;

	const struct kgsl_hwcg_reg *regs;

	int i, j;



	for (i = 0; i < ARRAY_SIZE(a5xx_hwcg_registers); i++) {

		if (a5xx_hwcg_registers[i].devfunc(adreno_dev))

			break;

	}



	if (i == ARRAY_SIZE(a5xx_hwcg_registers))

		return;



	regs = a5xx_hwcg_registers[i].regs;



	for (j = 0; j < a5xx_hwcg_registers[i].count; j++)

		kgsl_regwrite(device, regs[j].off, regs[j].val);



	/* enable top level HWCG */

	kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0xAAA8AA00);

	kgsl_regwrite(device, A5XX_RBBM_ISDB_CNT, 0x00000182);
@@ -1031,7 +1052,7 @@ static void _load_regfile(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = &adreno_dev->dev;

	const struct firmware *fw;

	uint32_t block_size, block_total = 0, fw_size;

	uint32_t block_size = 0, block_total = 0, fw_size;

	uint32_t *block;

	int ret = -EINVAL;
@@ -1420,12 +1441,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	/* Set the USE_RETENTION_FLOPS chicken bit */

	kgsl_regwrite(device, A5XX_CP_CHICKEN_DBG, 0x02000000);



	if (adreno_is_a530(adreno_dev) && !adreno_is_a530v1(adreno_dev))

		a5xx_hwcg_init(device, a530_hwcg_regs,

			ARRAY_SIZE(a530_hwcg_regs));

	else if (adreno_is_a510(adreno_dev))

		a5xx_hwcg_init(device, a510_hwcg_regs,

			ARRAY_SIZE(a510_hwcg_regs));

	a5xx_hwcg_init(adreno_dev);



	a5xx_protect_init(adreno_dev);

}

drivers/gpu/msm/adreno_dispatch.c

+9 −5
Original line number Diff line number Diff line
@@ -921,7 +921,7 @@ static void __adreno_dispatcher_preempt_trig_state( 
{

	struct adreno_dispatcher *dispatcher = &adreno_dev->dispatcher;

	struct kgsl_device *device = &(adreno_dev->dev);

	unsigned int rbbase;

	uint64_t rbbase;



	/*

	 * Hardware not yet idle means that preemption interrupt
@@ -944,7 +944,8 @@ static void __adreno_dispatcher_preempt_trig_state( 
	 * be device went idle w/o encountering any preempt token or

	 * we already preempted w/o interrupt

	 */

	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_BASE, &rbbase);

	adreno_readreg64(adreno_dev, ADRENO_REG_CP_RB_BASE,

			ADRENO_REG_CP_RB_BASE_HI, &rbbase);

	 /* Did preemption occur, if so then change states and return */

	if (rbbase != adreno_dev->cur_rb->buffer_desc.gpuaddr) {

		unsigned int val;
@@ -2081,7 +2082,8 @@ static int dispatcher_do_fault(struct kgsl_device *device) 
	struct adreno_dispatcher_cmdqueue *dispatch_q = NULL, *dispatch_q_temp;

	struct adreno_ringbuffer *rb;

	struct adreno_ringbuffer *hung_rb = NULL;

	unsigned int reg, base;

	unsigned int reg;

	uint64_t base;

	struct kgsl_cmdbatch *cmdbatch = NULL;

	int ret, i;

	int fault;
@@ -2121,7 +2123,8 @@ static int dispatcher_do_fault(struct kgsl_device *device) 
	/* hang opcode */

	kgsl_cffdump_hang(device);



	adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_BASE, &base);

	adreno_readreg64(adreno_dev, ADRENO_REG_CP_RB_BASE,

		ADRENO_REG_CP_RB_BASE_HI, &base);



	/*

	 * If the fault was due to a timeout then stop the CP to ensure we don't
@@ -2168,7 +2171,8 @@ static int dispatcher_do_fault(struct kgsl_device *device) 
	/* Set pagefault if it occurred */

	kgsl_mmu_set_pagefault(&device->mmu);



	adreno_readreg(adreno_dev, ADRENO_REG_CP_IB1_BASE, &base);

	adreno_readreg64(adreno_dev, ADRENO_REG_CP_IB1_BASE,

		ADRENO_REG_CP_IB1_BASE_HI, &base);



	/*

	 * Dump the snapshot information if this is the first

drivers/gpu/msm/adreno_perfcounter.c

+1 −1
Original line number Diff line number Diff line
@@ -408,7 +408,7 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev, 
		return 0;

	}



	t = min_t(int, group->reg_count, count);

	t = min_t(unsigned int, group->reg_count, count);



	buf = kmalloc(t * sizeof(unsigned int), GFP_KERNEL);

	if (buf == NULL) {