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Commit 6018bf02 authored by Len Brown's avatar Len Brown
Browse files

Merge branches 'acpi-idle', 'arm-idle' and 'intel-idle' into idle-remove-statedata

parents ac3ebafa 748f1177 b1beab48

arch/arm/mach-davinci/cpuidle.c

+25 −59
Original line number Diff line number Diff line
@@ -25,35 +25,44 @@ 


#define DAVINCI_CPUIDLE_MAX_STATES	2



struct davinci_ops {

	void (*enter) (u32 flags);

	void (*exit) (u32 flags);

	u32 flags;

};

static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);

static void __iomem *ddr2_reg_base;

static bool ddr2_pdown;



static void davinci_save_ddr_power(int enter, bool pdown)

{

	u32 val;



	val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);



	if (enter) {

		if (pdown)

			val |= DDR2_SRPD_BIT;

		else

			val &= ~DDR2_SRPD_BIT;

		val |= DDR2_LPMODEN_BIT;

	} else {

		val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);

	}



	__raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);

}



/* Actual code that puts the SoC in different idle states */

static int davinci_enter_idle(struct cpuidle_device *dev,

				struct cpuidle_driver *drv,

						int index)

{

	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];

	struct davinci_ops *ops = cpuidle_get_statedata(state_usage);



	if (ops && ops->enter)

		ops->enter(ops->flags);

	davinci_save_ddr_power(1, ddr2_pdown);



	index = cpuidle_wrap_enter(dev,	drv, index,

				arm_cpuidle_simple_enter);



	if (ops && ops->exit)

		ops->exit(ops->flags);

	davinci_save_ddr_power(0, ddr2_pdown);



	return index;

}



/* fields in davinci_ops.flags */

#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)



static struct cpuidle_driver davinci_idle_driver = {

	.name			= "cpuidle-davinci",

	.owner			= THIS_MODULE,
@@ -70,45 +79,6 @@ static struct cpuidle_driver davinci_idle_driver = { 
	.state_count = DAVINCI_CPUIDLE_MAX_STATES,

};



static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);

static void __iomem *ddr2_reg_base;



static void davinci_save_ddr_power(int enter, bool pdown)

{

	u32 val;



	val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);



	if (enter) {

		if (pdown)

			val |= DDR2_SRPD_BIT;

		else

			val &= ~DDR2_SRPD_BIT;

		val |= DDR2_LPMODEN_BIT;

	} else {

		val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);

	}



	__raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);

}



static void davinci_c2state_enter(u32 flags)

{

	davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));

}



static void davinci_c2state_exit(u32 flags)

{

	davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));

}



static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {

	[1] = {

		.enter	= davinci_c2state_enter,

		.exit	= davinci_c2state_exit,

	},

};



static int __init davinci_cpuidle_probe(struct platform_device *pdev)

{

	int ret;
@@ -124,11 +94,7 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev) 


	ddr2_reg_base = pdata->ddr2_ctlr_base;



	if (pdata->ddr2_pdown)

		davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;

	cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);



	device->state_count = DAVINCI_CPUIDLE_MAX_STATES;

	ddr2_pdown = pdata->ddr2_pdown;



	ret = cpuidle_register_driver(&davinci_idle_driver);

	if (ret) {

drivers/idle/intel_idle.c

+26 −49
Original line number Diff line number Diff line
@@ -108,6 +108,16 @@ static struct cpuidle_state *cpuidle_state_table; 
 */

#define CPUIDLE_FLAG_TLB_FLUSHED	0x10000



/*

 * MWAIT takes an 8-bit "hint" in EAX "suggesting"

 * the C-state (top nibble) and sub-state (bottom nibble)

 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.

 *

 * We store the hint at the top of our "flags" for each state.

 */

#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)

#define MWAIT2flg(eax) ((eax & 0xFF) << 24)



/*

 * States are indexed by the cstate number,

 * which is also the index into the MWAIT hint array.
@@ -118,21 +128,21 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C1 */

		.name = "C1-NHM",

		.desc = "MWAIT 0x00",

		.flags = CPUIDLE_FLAG_TIME_VALID,

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 3,

		.target_residency = 6,

		.enter = &intel_idle },

	{ /* MWAIT C2 */

		.name = "C3-NHM",

		.desc = "MWAIT 0x10",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 20,

		.target_residency = 80,

		.enter = &intel_idle },

	{ /* MWAIT C3 */

		.name = "C6-NHM",

		.desc = "MWAIT 0x20",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 200,

		.target_residency = 800,

		.enter = &intel_idle },
@@ -143,28 +153,28 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C1 */

		.name = "C1-SNB",

		.desc = "MWAIT 0x00",

		.flags = CPUIDLE_FLAG_TIME_VALID,

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle },

	{ /* MWAIT C2 */

		.name = "C3-SNB",

		.desc = "MWAIT 0x10",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 80,

		.target_residency = 211,

		.enter = &intel_idle },

	{ /* MWAIT C3 */

		.name = "C6-SNB",

		.desc = "MWAIT 0x20",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 104,

		.target_residency = 345,

		.enter = &intel_idle },

	{ /* MWAIT C4 */

		.name = "C7-SNB",

		.desc = "MWAIT 0x30",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 109,

		.target_residency = 345,

		.enter = &intel_idle },
@@ -175,28 +185,28 @@ static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C1 */

		.name = "C1-IVB",

		.desc = "MWAIT 0x00",

		.flags = CPUIDLE_FLAG_TIME_VALID,

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle },

	{ /* MWAIT C2 */

		.name = "C3-IVB",

		.desc = "MWAIT 0x10",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 59,

		.target_residency = 156,

		.enter = &intel_idle },

	{ /* MWAIT C3 */

		.name = "C6-IVB",

		.desc = "MWAIT 0x20",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 80,

		.target_residency = 300,

		.enter = &intel_idle },

	{ /* MWAIT C4 */

		.name = "C7-IVB",

		.desc = "MWAIT 0x30",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 87,

		.target_residency = 300,

		.enter = &intel_idle },
@@ -207,14 +217,14 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C1 */

		.name = "C1-ATM",

		.desc = "MWAIT 0x00",

		.flags = CPUIDLE_FLAG_TIME_VALID,

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 1,

		.target_residency = 4,

		.enter = &intel_idle },

	{ /* MWAIT C2 */

		.name = "C2-ATM",

		.desc = "MWAIT 0x10",

		.flags = CPUIDLE_FLAG_TIME_VALID,

		.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,

		.exit_latency = 20,

		.target_residency = 80,

		.enter = &intel_idle },
@@ -222,7 +232,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C4 */

		.name = "C4-ATM",

		.desc = "MWAIT 0x30",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 100,

		.target_residency = 400,

		.enter = &intel_idle },
@@ -230,41 +240,12 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { 
	{ /* MWAIT C6 */

		.name = "C6-ATM",

		.desc = "MWAIT 0x52",

		.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 140,

		.target_residency = 560,

		.enter = &intel_idle },

};



static long get_driver_data(int cstate)

{

	int driver_data;

	switch (cstate) {



	case 1:	/* MWAIT C1 */

		driver_data = 0x00;

		break;

	case 2:	/* MWAIT C2 */

		driver_data = 0x10;

		break;

	case 3:	/* MWAIT C3 */

		driver_data = 0x20;

		break;

	case 4:	/* MWAIT C4 */

		driver_data = 0x30;

		break;

	case 5:	/* MWAIT C5 */

		driver_data = 0x40;

		break;

	case 6:	/* MWAIT C6 */

		driver_data = 0x52;

		break;

	default:

		driver_data = 0x00;

	}

	return driver_data;

}



/**

 * intel_idle

 * @dev: cpuidle_device
@@ -278,8 +259,7 @@ static int intel_idle(struct cpuidle_device *dev, 
{

	unsigned long ecx = 1; /* break on interrupt flag */

	struct cpuidle_state *state = &drv->states[index];

	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];

	unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);

	unsigned long eax = flg2MWAIT(state->flags);

	unsigned int cstate;

	int cpu = smp_processor_id();
@@ -558,9 +538,6 @@ static int intel_idle_cpu_init(int cpu) 
		if (cpuidle_state_table[cstate].enter == NULL)

			continue;



		dev->states_usage[dev->state_count].driver_data =

			(void *)get_driver_data(cstate);



		dev->state_count += 1;

	}