drm/radeon: apply more strict limits for PLL params v2



Letting post and refernce divider get to big is bad for signal stability.

v2: increase the limit to 210

Signed-off-by: Christian König <christian.koenig@amd.com>

parent 6abc6d5c

drivers/gpu/drm/radeon/radeon_display.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
		}
		post_div = post_div_best;

		/* limit reference * post divider to a maximum */
		ref_div_max = min(210 / post_div, ref_div_max);

		/* get matching reference and feedback divider */
		ref_div = max(den / post_div, 1u);
		fb_div = nom;