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Commit 5f33b3bc authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Jeff Garzik
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pata_efar: fix PIO2 underclocking 



Fix the PIO mode 2 using mode 0 timings -- this driver should enable the
fast timing bank starting with PIO2, just like the PIIX/ICH drivers do.
Also, fix/rephrase some comments while at it.

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent 45bc955b

drivers/ata/pata_efar.c

+8 −9
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#include <linux/ata.h>



#define DRV_NAME	"pata_efar"

#define DRV_VERSION	"0.4.4"

#define DRV_VERSION	"0.4.5"



/**

 *	efar_pre_reset	-	Enable bits
@@ -98,18 +98,17 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) 
			    { 2, 1 },

			    { 2, 3 }, };



	if (pio > 2)

		control |= 1;	/* TIME1 enable */

	if (pio > 1)

		control |= 1;	/* TIME */

	if (ata_pio_need_iordy(adev))	/* PIO 3/4 require IORDY */

		control |= 2;	/* IE enable */

	/* Intel specifies that the PPE functionality is for disk only */

		control |= 2;	/* IE */

	/* Intel specifies that the prefetch/posting is for disk only */

	if (adev->class == ATA_DEV_ATA)

		control |= 4;	/* PPE enable */

		control |= 4;	/* PPE */



	pci_read_config_word(dev, idetm_port, &idetm_data);



	/* Enable PPE, IE and TIME as appropriate */



	/* Set PPE, IE, and TIME as appropriate */

	if (adev->devno == 0) {

		idetm_data &= 0xCCF0;

		idetm_data |= control;
@@ -129,7 +128,7 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) 
		pci_write_config_byte(dev, 0x44, slave_data);

	}



	idetm_data |= 0x4000;	/* Ensure SITRE is enabled */

	idetm_data |= 0x4000;	/* Ensure SITRE is set */

	pci_write_config_word(dev, idetm_port, idetm_data);

}