Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5f2f4d6e authored by Casey Piper's avatar Casey Piper Committed by Matt Wagantall
Browse files

clk: qcom: mdss: hdmi: increase delays to fix 20nm PLL lock failures 



Introduce minor delays in HDMI PHY sequence to ensure that
PHY is ready before failing with a timeout.

Change-Id: I8e9adf542b60e63c0c28d314afd5ac61fa64d1b2
Signed-off-by: default avatarCasey Piper <cpiper@codeaurora.org>
parent a85a579a

drivers/clk/msm/mdss/mdss-hdmi-pll-20nm.c

+4 −4
Original line number Diff line number Diff line
@@ -680,13 +680,13 @@ static int hdmi_20nm_vco_enable(struct clk *c) 
	struct mdss_pll_resources *io = vco->priv;



	MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000000);

	udelay(1);

	udelay(100);

	mb();

	MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000003);

	udelay(1);

	udelay(100);

	mb();

	MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000009);

	udelay(1);

	udelay(100);

	mb();



	/* Poll for C_READY and PHY READY */
@@ -695,7 +695,7 @@ static int hdmi_20nm_vco_enable(struct clk *c) 
	do {

		ready_poll = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_RESET_SM);

		time_out_loop++;

		udelay(1);

		udelay(10);

	} while (((ready_poll  & (1 << 6)) == 0) &&

		(time_out_loop < time_out_max));

	if (time_out_loop >= time_out_max)