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Commit 5f29d0a0 authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Nicolas Ferre
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ARM: at91: uncompress: autodetect the uart to use



This will now autodetect the first uart enabled by the bootloader
and will use it for uncompress. This will still assume that the bootloader
configured it (pins and clock).

This also allows to include all soc headers together.

Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent c40a763b
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+0 −53
Original line number Diff line number Diff line
@@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0
config HAVE_AT91_DBGU1
	bool

config HAVE_AT91_USART3
	bool

config HAVE_AT91_USART4
	bool

config HAVE_AT91_USART5
	bool

config AT91_SAM9_ALT_RESET
	bool
	default !ARCH_AT91X40
@@ -36,16 +27,12 @@ config ARCH_AT91RM9200
	select CPU_ARM920T
	select GENERIC_CLOCKEVENTS
	select HAVE_AT91_DBGU0
	select HAVE_AT91_USART3

config ARCH_AT91SAM9260
	bool "AT91SAM9260 or AT91SAM9XE"
	select CPU_ARM926T
	select GENERIC_CLOCKEVENTS
	select HAVE_AT91_DBGU0
	select HAVE_AT91_USART3
	select HAVE_AT91_USART4
	select HAVE_AT91_USART5
	select HAVE_NET_MACB

config ARCH_AT91SAM9261
@@ -74,7 +61,6 @@ config ARCH_AT91SAM9RL
	bool "AT91SAM9RL"
	select CPU_ARM926T
	select GENERIC_CLOCKEVENTS
	select HAVE_AT91_USART3
	select HAVE_FB_ATMEL
	select HAVE_AT91_DBGU0

@@ -83,16 +69,12 @@ config ARCH_AT91SAM9G20
	select CPU_ARM926T
	select GENERIC_CLOCKEVENTS
	select HAVE_AT91_DBGU0
	select HAVE_AT91_USART3
	select HAVE_AT91_USART4
	select HAVE_AT91_USART5
	select HAVE_NET_MACB

config ARCH_AT91SAM9G45
	bool "AT91SAM9G45 or AT91SAM9M10 families"
	select CPU_ARM926T
	select GENERIC_CLOCKEVENTS
	select HAVE_AT91_USART3
	select HAVE_FB_ATMEL
	select HAVE_NET_MACB
	select HAVE_AT91_DBGU1
@@ -526,41 +508,6 @@ config AT91_TIMER_HZ
	  system clock (of at least several MHz), rounding is less of a
	  problem so it can be safer to use a decimal values like 100.

choice
	prompt "Select a UART for early kernel messages"

config AT91_EARLY_DBGU0
	bool "DBGU on rm9200, 9260/9g20, 9261/9g10, 9rl and 9x5"
	depends on HAVE_AT91_DBGU0

config AT91_EARLY_DBGU1
	bool "DBGU on 9263 and 9g45"
	depends on HAVE_AT91_DBGU1

config AT91_EARLY_USART0
	bool "USART0"

config AT91_EARLY_USART1
	bool "USART1"

config AT91_EARLY_USART2
	bool "USART2"
	depends on ! ARCH_AT91X40

config AT91_EARLY_USART3
	bool "USART3"
	depends on HAVE_AT91_USART3

config AT91_EARLY_USART4
	bool "USART4"
	depends on HAVE_AT91_USART4

config AT91_EARLY_USART5
	bool "USART5"
	depends on HAVE_AT91_USART5

endchoice

endmenu

endif
+0 −5
Original line number Diff line number Diff line
@@ -88,11 +88,6 @@
#define AT91RM9200_BASE_RTC	0xfffffe00	/* Real-Time Clock */
#define AT91RM9200_BASE_MC	0xffffff00	/* Memory Controllers */

#define AT91_USART0	AT91RM9200_BASE_US0
#define AT91_USART1	AT91RM9200_BASE_US1
#define AT91_USART2	AT91RM9200_BASE_US2
#define AT91_USART3	AT91RM9200_BASE_US3

/*
 * Internal Memory.
 */
+0 −7
Original line number Diff line number Diff line
@@ -95,13 +95,6 @@
#define AT91SAM9260_BASE_WDT	0xfffffd40
#define AT91SAM9260_BASE_GPBR	0xfffffd50

#define AT91_USART0	AT91SAM9260_BASE_US0
#define AT91_USART1	AT91SAM9260_BASE_US1
#define AT91_USART2	AT91SAM9260_BASE_US2
#define AT91_USART3	AT91SAM9260_BASE_US3
#define AT91_USART4	AT91SAM9260_BASE_US4
#define AT91_USART5	AT91SAM9260_BASE_US5


/*
 * Internal Memory.
+0 −4
Original line number Diff line number Diff line
@@ -79,10 +79,6 @@
#define AT91SAM9261_BASE_WDT	0xfffffd40
#define AT91SAM9261_BASE_GPBR	0xfffffd50

#define AT91_USART0	AT91SAM9261_BASE_US0
#define AT91_USART1	AT91SAM9261_BASE_US1
#define AT91_USART2	AT91SAM9261_BASE_US2


/*
 * Internal Memory.
+0 −4
Original line number Diff line number Diff line
@@ -95,10 +95,6 @@
#define AT91SAM9263_BASE_RTT1	0xfffffd50
#define AT91SAM9263_BASE_GPBR	0xfffffd60

#define AT91_USART0	AT91SAM9263_BASE_US0
#define AT91_USART1	AT91SAM9263_BASE_US1
#define AT91_USART2	AT91SAM9263_BASE_US2

#define AT91_SMC	AT91_SMC0

/*
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