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Commit 5ebe8c23 authored by Shashank Mittal's avatar Shashank Mittal
Browse files

coresight: add STM driver support in upstream implementation 



Add STM driver in upstream implementation of Coresight driver.

This change copies drivers/coresight/coresight-stm.c (commit :
90095b2a) to driver/hwtracing/coresight
directory.

Change-Id: Id023bf85df0345205ca8baa6a97ff340d5808aeb
Signed-off-by: default avatarShashank Mittal <mittals@codeaurora.org>
parent 4850f699

drivers/hwtracing/coresight/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -58,4 +58,12 @@ config CORESIGHT_SOURCE_ETM3X 
	  which allows tracing the instructions that a processor is executing

	  This is primarily useful for instruction level tracing.  Depending

	  the ETM version data tracing may also be available.



config CORESIGHT_STM

	bool "CoreSight System Trace Macrocell driver"

	depends on CORESIGHT_LINKS_AND_SINKS

	help

	  This driver provides support for hardware assisted software

	  instrumentation based tracing. This is primarily useful for

	  logging useful software events or data.

endif

drivers/hwtracing/coresight/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -9,3 +9,4 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o 
obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \

					   coresight-replicator.o

obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o

obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o

drivers/hwtracing/coresight/coresight-priv.h

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 


#define TIMEOUT_US		100

#define BMVAL(val, lsb, msb)	((val & GENMASK(msb, lsb)) >> lsb)

#define BVAL(val, n)		((val & BIT(n)) >> n)



static inline void CS_LOCK(void __iomem *addr)

{

drivers/hwtracing/coresight/coresight-stm.c

0 → 100644
+906 −0

File added.

Preview size limit exceeded, changes collapsed.

include/linux/coresight.h

+7 −0
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@@ -43,6 +43,13 @@ 


extern struct bus_type coresight_bustype;



enum coresight_clk_rate {

	CORESIGHT_CLK_RATE_OFF,

	CORESIGHT_CLK_RATE_TRACE = 1000,

	CORESIGHT_CLK_RATE_HSTRACE = 2000,

	CORESIGHT_CLK_RATE_FIXED = 3000,

};



enum coresight_dev_type {

	CORESIGHT_DEV_TYPE_NONE,

	CORESIGHT_DEV_TYPE_SINK,