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Commit 5e790fd0 authored by Jack Pham's avatar Jack Pham
Browse files

usb: dwc3: Use HIRD and LPM parameters from upstream 



Upstream changes added similar device tree bindings for
specifying HIRD and LPM NYET threshold values. Use those
instead and remove the bindings we added. Make the switch
in the existing device trees as well.

Change-Id: I646eab14e8b7f4bebd48b189859ba10b8ea20aa3
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent bc7fbfa6

Documentation/devicetree/bindings/usb/dwc3.txt

+0 −5
Original line number Diff line number Diff line
@@ -17,13 +17,8 @@ Optional properties: 
 - snps,nominal-elastic-buffer: When set, the nominal elastic buffer setting

	is used. By default, the half-full setting is used.

 - snps,usb3-u1u2-disable: If present, disable u1u2 low power modes for DWC3 core controller in SS mode.

 - snps,hird_thresh: If present, will determine the value of DCTL[HIRD_Thresh] which, in turn,

	controls the UTMI sleep mechanism vs. the PHY. Default value is 12.

 - snps,bus-suspend-enable: If present then controller supports low power mode

	during bus suspend.

 - snps,lpm-nyet-thresh: If present, will determine the value of DCTL[LPM_NYET_Thres].

	If BESL value received from the host in the LPM token is less than this value we send LPM ACK to

	the host. Otherwise the device returns LPM NYET.

 - snps,disable-clk-gating: If present, disable controller's internal clock gating. Default it is enabled.

 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled

 - snps,lpm-nyet-threshold: LPM NYET threshold

arch/arm/boot/dts/qcom/mdm9640.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -653,8 +653,9 @@ 
			snps,nominal-elastic-buffer;

			snps,hsphy-auto-suspend-disable;

			snps,ssphy-auto-suspend-disable;

			snps,hird_thresh = <0x7>;

			snps,lpm-nyet-thresh = <0x8>;

			snps,has-lpm-erratum;

			snps,lpm-nyet-threshold = /bits/ 8 <0x8>;

			snps,hird-threshold = /bits/ 8 <0x7>;

			snps,bus-suspend-enable;

			snps,usb3-u1u2-disable;

		};

arch/arm/boot/dts/qcom/msm8996.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -2062,7 +2062,8 @@ 
			tx-fifo-resize;

			snps,usb3-u1u2-disable;

			snps,nominal-elastic-buffer;

			snps,hird_thresh = <0x10>;

			snps,is-utmi-l1-suspend;

			snps,hird-threshold = /bits/ 8 <0x0>;

		};



		qcom,usbbam@6b04000 {
@@ -2163,7 +2164,8 @@ 
			usb-phy = <&qusb_phy1>, <&usb_nop_phy>;

			maximum-speed = "high-speed";

			snps,nominal-elastic-buffer;

			snps,hird_thresh = <0x10>;

			snps,is-utmi-l1-suspend;

			snps,hird-threshold = /bits/ 8 <0x0>;

		};

	};

drivers/usb/dwc3/core.c

+0 −15
Original line number Diff line number Diff line
@@ -45,8 +45,6 @@ 


#include "debug.h"



#define DWC3_DCTL_HIRD_THRES_DEFAULT	12



/* -------------------------------------------------------------------------- */



void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
@@ -793,9 +791,6 @@ static int dwc3_probe(struct platform_device *pdev) 
	void __iomem		*regs;

	void			*mem;



	u32			hird_thresh;

	u32			lpm_nyet_thresh;



	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);

	if (!mem)

		return -ENOMEM;
@@ -875,16 +870,6 @@ static int dwc3_probe(struct platform_device *pdev) 
				"snps,usb3-u1u2-disable");

		dwc->enable_bus_suspend = of_property_read_bool(node,

						"snps,bus-suspend-enable");

		ret = of_property_read_u32(node, "snps,hird_thresh", &hird_thresh);

		if (!ret)

			dwc->hird_thresh = (u8) hird_thresh;

		else

			dwc->hird_thresh = DWC3_DCTL_HIRD_THRES_DEFAULT;



		ret = of_property_read_u32(node, "snps,lpm-nyet-thresh",

							&lpm_nyet_thresh);

		if (!ret)

			dwc->lpm_nyet_thresh = (u8)lpm_nyet_thresh;



		dwc->disable_clk_gating = of_property_read_bool(node,

					"snps,disable-clk-gating");

drivers/usb/dwc3/core.h

+0 −7
Original line number Diff line number Diff line
@@ -267,9 +267,6 @@ 


#define DWC3_DCTL_APPL1RES	(1 << 23)



#define DWC3_DCTL_LPM_NYET_THRES_MASK	(0x0f << 20)

#define DWC3_DCTL_LPM_NYET_THRES(n)	((n) << 20)



/* These apply for core versions 1.87a and earlier */

#define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)

#define DWC3_DCTL_TRGTULST(n)		((n) << 17)
@@ -805,8 +802,6 @@ struct dwc3_scratchpad_array { 
 * @is_drd: device supports dual-role or not

 * @err_evt_seen: previous event in queue was erratic error

 * @usb3_u1u2_disable: if true, disable U1U2 low power modes in Superspeed mode.

 * @hird_thresh: value to configure in DCTL[HIRD_Thresh]

 * @lpm_nyet_thresh: value to configure in DCTL[LPM_NYET_Thresh]

 * @in_lpm: if 1, indicates that the controller is in low power mode (no clocks)

 * @tx_fifo_size: Available RAM size for TX fifo allocation

 * @irq: irq number
@@ -945,8 +940,6 @@ struct dwc3 { 


	struct dwc3_gadget_events	dbg_gadget_events;



	u8			hird_thresh;

	u8			lpm_nyet_thresh;

	atomic_t		in_lpm;

	int			tx_fifo_size;

	bool			b_suspend;