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Commit 5e329e47 authored by Marc Zyngier's avatar Marc Zyngier Committed by Gerrit - the friendly Code Review server
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FROMLIST: arm64: Move post_ttbr_update_workaround to C code 



We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git


 commit 400a169447ad2268b023637a118fba27246bcc19)

Change-Id: Ic21e59001470a2e88db7291eb5f6393f8a64a7dd
[ghackmann@google.com: 3.18 doesn't support CPUs that need the Cavium
 errata, so for now post_ttbr_update_workaround() is an empty stub that
 will be used in a later patch series.]
Signed-off-by: default avatarGreg Hackmann <ghackmann@google.com>
Git-Commit: 0bfb4642
Git-repo: git://android.googlesource.com/kernel/common.git


Signed-off-by: default avatarVinayak Menon <vinmenon@codeaurora.org>
parent c75b5858

arch/arm64/kernel/entry.S

+10 −0
Original line number Diff line number Diff line
@@ -213,6 +213,16 @@ alternative_else_nop_endif 
	.endif



	__uaccess_ttbr0_enable x0, x1



	.if	\el == 0

	/*

	 * Enable errata workarounds only if returning to user. The only

	 * workaround currently required for TTBR0_EL1 changes are for the

	 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache

	 * corruption).

	 */

	bl	post_ttbr_update_workaround

	.endif

1:

	.if	\el != 0

	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit

arch/arm64/mm/context.c

+5 −0
Original line number Diff line number Diff line
@@ -199,6 +199,11 @@ switch_mm_fastpath: 
		cpu_switch_mm(mm->pgd, mm);

}



/* Errata workaround post TTBRx_EL1 update. */

asmlinkage void post_ttbr_update_workaround(void)

{

}



static int asids_init(void)

{

	int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 4);

arch/arm64/mm/proc.S

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ ENTRY(cpu_do_switch_mm) 
	isb

	msr	ttbr0_el1, x0			// now update TTBR0

	isb

	ret

	b	post_ttbr_update_workaround	// Back to C code...

ENDPROC(cpu_do_switch_mm)



	.section ".text.init", #alloc, #execinstr