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Commit 5df22a61 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu into next/soc 

Merge "ARM: mvebu: SoC changes for v3.16" from Jason Cooper:

mvebu SoC changes for v3.16

 - Armada 375/38x coherency support
 - Armada 375/38x SMP support
 - mvebu PMSU and CPU reset support
 - Armada 370/XP cpuidle support
 - kirkwood remove platform init of audio device
 - small fixes and cleanup for new SoC (375/38x)

Note:
 - due to complex deps, cpuidle changes Acked by appropriate maintainer for
   going though arm-soc tree.

* tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu

: (46 commits)
  ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
  ARM: mvebu: conditionalize Armada 375 coherency workaround
  ARM: mvebu: conditionalize Armada 375 SMP workaround
  ARM: mvebu: add Armada 375 A0 revision definition
  ARM: mvebu: initialize mvebu-soc-id earlier
  ARM: mvebu: fix thermal quirk SoC revision check
  ARM: Kirkwood: t5325: Remove platform device to instantiate audio
  ARM: Kirkwood: Remove platform driver for codec
  ARM: mvebu: Add thermal quirk for the Armada 375 DB board
  ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
  ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
  ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
  ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
  cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
  ARM: mvebu: Register notifier callback for the cpuidle transition
  ARM: mvebu: refine which files are build in mach-mvebu
  ARM: mvebu: Add the PMSU related part of the cpu idle functions
  ARM: mvebu: Allow to power down L2 cache controller in idle mode
  ARM: mvebu: Low level function to disable HW coherency support
  ARM: mvebu: Split low level functions to manipulate HW coherency
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c15c1199 9f0affcf

Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt

+10 −9
Original line number Diff line number Diff line 
Power Management Service Unit(PMSU)

-----------------------------------

Available on Marvell SOCs: Armada 370 and Armada XP

Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP



Required properties:



- compatible: "marvell,armada-370-xp-pmsu"

- compatible: should be one of:

  - "marvell,armada-370-pmsu" for Armada 370 or Armada XP

  - "marvell,armada-380-pmsu" for Armada 38x

  - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now

    deprecated and will be removed



- reg: Should contain PMSU registers location and length. First pair

  for the per-CPU SW Reset Control registers, second pair for the

  Power Management Service Unit.

- reg: Should contain PMSU registers location and length.



Example:



armada-370-xp-pmsu@d0022000 {

	compatible = "marvell,armada-370-xp-pmsu";

	reg = <0xd0022100 0x430>,

	      <0xd0020800 0x20>;

armada-370-xp-pmsu@22000 {

	compatible = "marvell,armada-370-pmsu";

	reg = <0x22000 0x1000>;

};

Documentation/devicetree/bindings/arm/armada-cpu-reset.txt

0 → 100644
+14 −0
Original line number Diff line number Diff line 
Marvell Armada CPU reset controller

===================================



Required properties:



- compatible: Should be "marvell,armada-370-cpu-reset".



- reg: should be register base and length as documented in the

  datasheet for the CPU reset registers



cpurst: cpurst@20800 {

       compatible = "marvell,armada-370-cpu-reset";

       reg = <0x20800 0x20>;

};

Documentation/devicetree/bindings/arm/coherency-fabric.txt

+27 −5
Original line number Diff line number Diff line 
Coherency fabric

----------------

Available on Marvell SOCs: Armada 370 and Armada XP

Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP



Required properties:



- compatible: "marvell,coherency-fabric"

- compatible: the possible values are:



 * "marvell,coherency-fabric", to be used for the coherency fabric of

   the Armada 370 and Armada XP.



 * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency

   fabric.



 * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency

   fabric.



- reg: Should contain coherency fabric registers location and

  length. First pair for the coherency fabric registers, second pair

  for the per-CPU fabric registers registers.

  length.



 * For "marvell,coherency-fabric", the first pair for the coherency

   fabric registers, second pair for the per-CPU fabric registers.



Example:

 * For "marvell,armada-375-coherency-fabric", only one pair is needed

   for the per-CPU fabric registers.



 * For "marvell,armada-380-coherency-fabric", only one pair is needed

   for the per-CPU fabric registers.



Examples:



coherency-fabric@d0020200 {

	compatible = "marvell,coherency-fabric";
@@ -19,3 +36,8 @@ coherency-fabric@d0020200 { 


};



coherency-fabric@21810 {

	compatible = "marvell,armada-375-coherency-fabric";

	reg = <0x21810 0x1c>;

};

Documentation/devicetree/bindings/arm/cpus.txt

+3 −0
Original line number Diff line number Diff line
@@ -185,6 +185,9 @@ nodes to be present and contain the properties described below. 
			    "qcom,gcc-msm8660"

			    "qcom,kpss-acc-v1"

			    "qcom,kpss-acc-v2"

			    "marvell,armada-375-smp"

			    "marvell,armada-380-smp"

			    "marvell,armada-xp-smp"



	- cpu-release-addr

		Usage: required for systems that have an "enable-method"

arch/arm/mach-kirkwood/board-dt.c

+1 −1
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ static void __init kirkwood_dt_init(void) 
{

	kirkwood_disable_mbus_error_propagation();



	BUG_ON(mvebu_mbus_dt_init());

	BUG_ON(mvebu_mbus_dt_init(false));



#ifdef CONFIG_CACHE_FEROCEON_L2

	feroceon_of_init();