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Commit 5d8dd35f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: camera: update CPHY settings"

parents 9056a6df fa9a97f4

drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.c

+8 −6
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static void msm_csid_set_debug_reg(struct csid_device *csid_dev, 
	msm_camera_io_w(val, csid_dev->base +

		csid_dev->ctrl_reg->csid_reg.csid_irq_clear_cmd_addr);

}

#elseif(SHORT_PKT_CAPTURE)

#elif(SHORT_PKT_CAPTURE)

static void msm_csid_set_debug_reg(struct csid_device *csid_dev,

	struct msm_camera_csid_params *csid_params)

{
@@ -314,8 +314,8 @@ static int msm_csid_config(struct csid_device *csid_dev, 
			val |= csid_params->phy_sel <<

			    csid_dev->ctrl_reg->csid_reg.csid_phy_sel_shift_3p;

			val |= ENABLE_3P_BIT;

			msm_camera_io_w(val, csidbase +

			    csid_dev->ctrl_reg->csid_reg.csid_3p_ctrl_0_addr);

			msm_camera_io_w(val, csidbase + csid_dev->ctrl_reg

				->csid_reg.csid_3p_ctrl_0_addr);

		}

	}
@@ -338,6 +338,7 @@ static irqreturn_t msm_csid_irq(int irq_num, void *data) 
{

	uint32_t irq;

	uint32_t short_dt = 0;

	uint32_t count = 0, dt = 0;

	struct csid_device *csid_dev = data;



	if (!csid_dev) {
@@ -355,9 +356,10 @@ static irqreturn_t msm_csid_irq(int irq_num, void *data) 
		short_dt = msm_camera_io_r(csid_dev->base +

			csid_dev->ctrl_reg->

			csid_reg.csid_captured_short_pkt_addr);

		short_dt = short_dt >> 24;

		pr_err("CSID:: %s:%d core %d short dt %x\n",

			__func__, __LINE__, csid_dev->pdev->id, short_dt);

		count = (short_dt >> 8) & 0xffff;

		dt =  short_dt >> 24;

		CDBG("CSID:: %s:%d core %d dt: 0x%x, count: %d\n",

			__func__, __LINE__, csid_dev->pdev->id, dt, count);

		msm_camera_io_w(0x101, csid_dev->base +

		csid_dev->ctrl_reg->csid_reg.csid_rst_cmd_addr);

	}

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_3_5_hwreg.h

+20 −1
Original line number Diff line number Diff line
@@ -28,18 +28,37 @@ struct csiphy_reg_3ph_parms_t csiphy_v3_5_3ph = { 
	0x188,

	0x18C,

	0x190,

	0x104,

	0x108,

	0x10c,

	0x114,

	0x118,

	0x11c,

	0x120,

	0x124,

	0x128,

	0x12c,

	0x130,

	0x134,

	0x138,

	0x13C,

	0x140,

	0x144,

	0x148,

	0x14C,

	0x154,

	0x15C,

	0x160,

	0x1cc,

	0x164,

	0x168,

	0x16C,

	0x170,

	0x174,

	0x178,

	0x17C,

	0x180,

	0x184,

	0x1cc,

	0x81c,

	0x82c,

	0x830,

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+69 −17
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#define MAX_LANES                                   4

#define CLOCK_OFFSET                              0x700

#define CLK_MISS_TIMER                            0xA5

#define GLITCH_ELIMINATION_NUM                    0x12 /* bit [6:4] */



#undef CDBG

#define CDBG(fmt, args...) pr_debug(fmt, ##args)
@@ -124,23 +125,31 @@ static int msm_csiphy_3phase_lane_config( 
			lane_mask >>= 1;

			continue;

		}



		msm_camera_io_w(0x0,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl21_addr + 0x200*i);

		msm_camera_io_w(0x33,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl23_addr + 0x200*i);

		msm_camera_io_w(0xA0,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl26_addr + 0x200*i);

		msm_camera_io_w(0x17,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl27_addr + 0x200*i);

		msm_camera_io_w(0x6,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl1_addr + 0x200*i);

		msm_camera_io_w(((csiphy_params->settle_cnt >> 8) & 0xff),

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl2_addr + 0x200*i);

		msm_camera_io_w((csiphy_params->settle_cnt & 0xff),

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl3_addr + 0x200*i);



		msm_camera_io_w(0x0,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl34_addr + 0x200*i);

		msm_camera_io_w(0x7F,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl35_addr + 0x200*i);

		msm_camera_io_w(0x7F,

		msm_camera_io_w(0x20,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl36_addr + 0x200*i);



			mipi_csiphy_3ph_lnn_ctrl5_addr + 0x200*i);

		msm_camera_io_w(0x3e,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl6_addr + 0x200*i);
@@ -159,33 +168,74 @@ static int msm_csiphy_3phase_lane_config( 
		msm_camera_io_w(0x0,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl11_addr + 0x200*i);



		msm_camera_io_w(0x50,

		msm_camera_io_w(0x1,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl12_addr + 0x200*i);

		msm_camera_io_w(0x10,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl15_addr + 0x200*i);

		msm_camera_io_w(0x1,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl16_addr + 0x200*i);

		msm_camera_io_w(GLITCH_ELIMINATION_NUM,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl17_addr + 0x200*i);

		msm_camera_io_w(0xFE,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl18_addr + 0x200*i);

		msm_camera_io_w(0x1,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl19_addr + 0x200*i);

		msm_camera_io_w(0x33,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl23_addr + 0x200*i);

		msm_camera_io_w(ULPM_WAKE_UP_TIMER_MODE,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl24_addr + 0x200*i);

		if (ULPM_WAKE_UP_TIMER_MODE == 0x22) {

		msm_camera_io_w(0x41,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl28_addr + 0x200*i);

		msm_camera_io_w(0x41,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl29_addr + 0x200*i);

		msm_camera_io_w(0x3E,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl30_addr + 0x200*i);

		msm_camera_io_w(0x7F,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl33_addr + 0x200*i);

		msm_camera_io_w(0x7F,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl34_addr + 0x200*i);

		msm_camera_io_w(0x7F,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl35_addr + 0x200*i);

		msm_camera_io_w(0x0,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl36_addr + 0x200*i);



		if (ULPM_WAKE_UP_TIMER_MODE == 0x22) {

			msm_camera_io_w(0x10,

				csiphybase + csiphy_dev->ctrl_reg->

				csiphy_3ph_reg.mipi_csiphy_3ph_lnn_ctrl51_addr +

				0x200*i);

		}

		msm_camera_io_w(0x20,

		msm_camera_io_w(0x48,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_lnn_ctrl25_addr + 0x200*i);



		lane_mask >>= 1;

		i++;

	}

	if (csiphy_params->combo_mode == 1)

	if (csiphy_params->combo_mode == 1) {

		msm_camera_io_w(0x2,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_cmn_ctrl7_addr);

	else

	} else {

		msm_camera_io_w(0x6,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.

			mipi_csiphy_3ph_cmn_ctrl7_addr);

	}

	/* Delay for stabilizing the regulator*/

	usleep_range(10, 15);

	msm_csiphy_cphy_irq_config(csiphy_dev, csiphy_params);
@@ -777,6 +827,7 @@ ioremap_fail: 
static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)

{

	int i = 0;

	int rc = 0;

	struct msm_camera_csi_lane_params *csi_lane_params;

	uint16_t csi_lane_mask;

	csi_lane_params = (struct msm_camera_csi_lane_params *)arg;
@@ -999,6 +1050,7 @@ static int32_t msm_csiphy_cmd(struct csiphy_device *csiphy_dev, void *arg) 
		pr_err("%s: csiphy_dev NULL\n", __func__);

		return -EINVAL;

	}



	switch (cdata->cfgtype) {

	case CSIPHY_INIT:

		rc = msm_csiphy_init(csiphy_dev);
@@ -1304,7 +1356,7 @@ static int csiphy_probe(struct platform_device *pdev) 
		new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V35;

		new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;

	} else {

		pr_err("%s:%d, invalid hw version : 0x%x", __func__, __LINE__,

		pr_err("%s:%d, invalid hw version : 0x%x\n", __func__, __LINE__,

		new_csiphy_dev->hw_dts_version);

		return -EINVAL;

	}

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h

+20 −1
Original line number Diff line number Diff line
@@ -60,18 +60,37 @@ struct csiphy_reg_3ph_parms_t { 
	uint32_t mipi_csiphy_3ph_lnn_ctrl34_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl35_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl36_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl1_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl2_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl3_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl5_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl6_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl7_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl8_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl9_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl10_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl11_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl12_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl13_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl14_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl15_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl16_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl17_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl18_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl19_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl21_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl23_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl24_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl51_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl25_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl26_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl27_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl28_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl29_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl30_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl31_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl32_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl33_addr;

	uint32_t mipi_csiphy_3ph_lnn_ctrl51_addr;

	uint32_t mipi_csiphy_3ph_cmn_ctrl7_addr;

	uint32_t mipi_csiphy_3ph_cmn_ctrl11_addr;

	uint32_t mipi_csiphy_3ph_cmn_ctrl12_addr;