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Commit 5d3fed70 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "Business as usual for SPI - some new drivers, lots of fixes and
  updates to existing drivers plus some new framework features.  Notable
  changes are:

   - Support for dual and quad data lines, commonly used by flash chips
     to improve performance, from Wang Yuhang.
   - Factored out a common pattern for runtime PM implementation into
     the core saving a bunch of code.
   - A particularly nice set of updates to the ep93xx driver from
     H Hartley Sweeten, modernising it and reducing the code size a lot.
   - New drivers for Blackfin v3, EFM32, Freescale DSPI and TI QSPI"

* tag 'spi-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (133 commits)
  spi/qspi: fix missing unlock on error in ti_qspi_start_transfer_one()
  spi: quad: fix the name of DT property
  spi: core: Fix spi_register_master error handling
  spi: efm32: Fix build error
  spi: altera: Use DIV_ROUND_UP to calculate hw->bytes_per_word
  spi: rspi: Add spi_master_get() call to prevent use after free
  spi: quad: Make DT properties optional
  spi: quad: Fix missing return
  spi: Use dev_get_drvdata at appropriate places
  spi: use dev_get_platdata()
  spi: nuc900: Fix mode_bits setting
  spi: simplify devm_request_mem_region/devm_ioremap
  spi: altera: Simplify altera_spi_txrx implementation for noirq case
  spi: spi-rspi: fix inconsistent spin_lock_irqsave
  spi/qspi: Add compatible string for am4372.
  spi/qspi: Fix device table entry
  spi/sirf: fix the misunderstanding about len of spi_transfer
  spi/qspi: Add dual/quad spi read support
  spi: sirf: fix error return code in spi_sirfsoc_probe()
  spi: bcm2835: Add spi_master_get() call to prevent use after free
  ...
parents 8243b7f5 57873925

Documentation/devicetree/bindings/spi/efm32-spi.txt

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* Energy Micro EFM32 SPI



Required properties:

- #address-cells: see spi-bus.txt

- #size-cells: see spi-bus.txt

- compatible: should be "efm32,spi"

- reg: Offset and length of the register set for the controller

- interrupts: pair specifying rx and tx irq

- clocks: phandle to the spi clock

- cs-gpios: see spi-bus.txt

- location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.



Example:



spi1: spi@0x4000c400 { /* USART1 */

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "efm32,spi";

	reg = <0x4000c400 0x400>;

	interrupts = <15 16>;

	clocks = <&cmu 20>;

	cs-gpios = <&gpio 51 1>; // D3

	location = <1>;

	status = "ok";



	ks8851@0 {

		compatible = "ks8851";

		spi-max-frequency = <6000000>;

		reg = <0>;

		interrupt-parent = <&boardfpga>;

		interrupts = <4>;

		status = "ok";

	};

};

Documentation/devicetree/bindings/spi/spi-bus.txt

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@@ -55,6 +55,16 @@ contain the following properties. 
    		chip select active high

- spi-3wire       - (optional) Empty property indicating device requires

    		    3-wire mode.

- spi-tx-bus-width - (optional) The bus width(number of data wires) that

                      used for MOSI. Defaults to 1 if not present.

- spi-rx-bus-width - (optional) The bus width(number of data wires) that

                      used for MISO. Defaults to 1 if not present.



Some SPI controllers and devices support Dual and Quad SPI transfer mode.

It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).

Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is

only 1(SINGLE), 2(DUAL) and 4(QUAD).

Dual/Quad mode is not allowed when 3-wire mode is used.



If a gpio chipselect is used for the SPI slave the gpio number will be passed

via the cs_gpio

Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt

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ARM Freescale DSPI controller



Required properties:

- compatible : "fsl,vf610-dspi"

- reg : Offset and length of the register set for the device

- interrupts : Should contain SPI controller interrupt

- clocks: from common clock binding: handle to dspi clock.

- clock-names: from common clock binding: Shall be "dspi".

- pinctrl-0: pin control group to be used for this controller.

- pinctrl-names: must contain a "default" entry.

- spi-num-chipselects : the number of the chipselect signals.

- bus-num : the slave chip chipselect signal number.

Example:



dspi0@4002c000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "fsl,vf610-dspi";

	reg = <0x4002c000 0x1000>;

	interrupts = <0 67 0x04>;

	clocks = <&clks VF610_CLK_DSPI0>;

	clock-names = "dspi";

	spi-num-chipselects = <5>;

	bus-num = <0>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_dspi0_1>;

	status = "okay";



	sflash: at26df081a@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "atmel,at26df081a";

		spi-max-frequency = <16000000>;

		spi-cpol;

		spi-cpha;

		reg = <0>;

		linux,modalias = "m25p80";

		modal = "at26df081a";

	};

};

Documentation/devicetree/bindings/spi/ti_qspi.txt

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TI QSPI controller.



Required properties:

- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".

- reg: Should contain QSPI registers location and length.

- #address-cells, #size-cells : Must be present if the device has sub-nodes

- ti,hwmods: Name of the hwmod associated to the QSPI



Recommended properties:

- spi-max-frequency: Definition as per

                     Documentation/devicetree/bindings/spi/spi-bus.txt



Example:



qspi: qspi@4b300000 {

	compatible = "ti,dra7xxx-qspi";

	reg = <0x4b300000 0x100>;

	#address-cells = <1>;

	#size-cells = <0>;

	spi-max-frequency = <25000000>;

	ti,hwmods = "qspi";

};

Documentation/spi/spi-summary

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@@ -215,7 +215,7 @@ So for example arch/.../mach-*/board-*.c files might have code like: 
	/* if your mach-* infrastructure doesn't support kernels that can

	 * run on multiple boards, pdata wouldn't benefit from "__init".

	 */

	static struct mysoc_spi_data __initdata pdata = { ... };

	static struct mysoc_spi_data pdata __initdata = { ... };



	static __init board_init(void)

	{