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Commit 5d1190ea authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
Browse files

arm: mach-orion5x: convert to use mvebu-mbus driver 



This commit migrates the mach-orion5x platforms to use the mvebu-mbus
driver and therefore removes the Orion5x-specific addr-map code.

The dove_init_early() function now initializes the mvebu-mbus driver
by calling mvebu_mbus_init().

We also convert a number of orion5x_setup_xyz_win() calls to the
appropriate mvebu_mbus_add_window() calls, as each board was doing its
own setup for the NOR window or other devices. Ultimately, those
devices will be probed from the DT.

The common address decoding windows are now registered in the
orion5x_setup_wins() function. It is worth noting that the four PCIe
address decoding windows will ultimately no longer have to be
registered here: it will be done automatically by the PCIe driver once
Dove has been migrated to use the upcoming mvebu PCIe driver.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 7d554902

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -600,6 +600,7 @@ config ARCH_ORION5X 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell Orion 5x series SoCs:

	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),

arch/arm/mach-orion5x/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y				+= common.o addr-map.o pci.o irq.o mpp.o

obj-y				+= common.o pci.o irq.o mpp.o

obj-$(CONFIG_MACH_DB88F5281)	+= db88f5281-setup.o

obj-$(CONFIG_MACH_RD88F5182)	+= rd88f5182-setup.o

obj-$(CONFIG_MACH_KUROBOX_PRO)	+= kurobox_pro-setup.o

arch/arm/mach-orion5x/addr-map.c

deleted100644 → 0
+0 −155
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-orion5x/addr-map.c

 *

 * Address map functions for Marvell Orion 5x SoCs

 *

 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/mbus.h>

#include <linux/io.h>

#include <mach/hardware.h>

#include <plat/addr-map.h>

#include "common.h"



/*

 * The Orion has fully programmable address map. There's a separate address

 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,

 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own

 * address decode windows that allow it to access any of the Orion resources.

 *

 * CPU address decoding --

 * Linux assumes that it is the boot loader that already setup the access to

 * DDR and internal registers.

 * Setup access to PCI and PCIe IO/MEM space is issued by this file.

 * Setup access to various devices located on the device bus interface (e.g.

 * flashes, RTC, etc) should be issued by machine-setup.c according to

 * specific board population (by using orion5x_setup_*_win()).

 *

 * Non-CPU Masters address decoding --

 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR

 * banks only (the typical use case).

 * Setup access for each master to DDR is issued by platform device setup.

 */



/*

 * Generic Address Decode Windows bit settings

 */

#define TARGET_DEV_BUS		1

#define TARGET_PCI		3

#define TARGET_PCIE		4

#define TARGET_SRAM		9

#define ATTR_PCIE_MEM		0x59

#define ATTR_PCIE_IO		0x51

#define ATTR_PCIE_WA		0x79

#define ATTR_PCI_MEM		0x59

#define ATTR_PCI_IO		0x51

#define ATTR_DEV_CS0		0x1e

#define ATTR_DEV_CS1		0x1d

#define ATTR_DEV_CS2		0x1b

#define ATTR_DEV_BOOT		0xf

#define ATTR_SRAM		0x0



static int __initdata win_alloc_count;



static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,

		  const int win)

{

	u32 dev, rev;



	orion5x_pcie_id(&dev, &rev);

	if ((dev == MV88F5281_DEV_ID && win < 4)

	    || (dev == MV88F5182_DEV_ID && win < 2)

	    || (dev == MV88F5181_DEV_ID && win < 2)

	    || (dev == MV88F6183_DEV_ID && win < 4))

		return 1;



	return 0;

}



/*

 * Description of the windows needed by the platform code

 */

static struct orion_addr_map_cfg addr_map_cfg __initdata = {

	.num_wins = 8,

	.cpu_win_can_remap = cpu_win_can_remap,

	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,

};



static const struct __initdata orion_addr_map_info addr_map_info[] = {

	/*

	 * Setup windows for PCI+PCIe IO+MEM space.

	 */

	{ 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,

	  TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE

	},

	{ 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,

	  TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE

	},

	{ 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,

	  TARGET_PCIE, ATTR_PCIE_MEM, -1

	},

	{ 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,

	  TARGET_PCI, ATTR_PCI_MEM, -1

	},

	/* End marker */

	{ -1, 0, 0, 0, 0, 0 }

};



void __init orion5x_setup_cpu_mbus_bridge(void)

{

	/*

	 * Disable, clear and configure windows.

	 */

	orion_config_wins(&addr_map_cfg, addr_map_info);

	win_alloc_count = 4;



	/*

	 * Setup MBUS dram target info.

	 */

	orion_setup_cpu_mbus_target(&addr_map_cfg,

				    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);

}



void __init orion5x_setup_dev_boot_win(u32 base, u32 size)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,

			    TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);

}



void __init orion5x_setup_dev0_win(u32 base, u32 size)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,

			    TARGET_DEV_BUS, ATTR_DEV_CS0, -1);

}



void __init orion5x_setup_dev1_win(u32 base, u32 size)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,

			    TARGET_DEV_BUS, ATTR_DEV_CS1, -1);

}



void __init orion5x_setup_dev2_win(u32 base, u32 size)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,

			    TARGET_DEV_BUS, ATTR_DEV_CS2, -1);

}



void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,

			    TARGET_PCIE, ATTR_PCIE_WA, -1);

}



void __init orion5x_setup_sram_win(void)

{

	orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,

			    ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,

			    TARGET_SRAM, ATTR_SRAM, -1);

}

arch/arm/mach-orion5x/board-dt.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ static void __init orion5x_dt_init(void) 
	/*

	 * Setup Orion address map

	 */

	orion5x_setup_cpu_mbus_bridge();

	orion5x_setup_wins();



	/* Setup root of clk tree */

	clk_init();

arch/arm/mach-orion5x/common.c

+46 −3
Original line number Diff line number Diff line
@@ -34,7 +34,6 @@ 
#include <linux/platform_data/usb-ehci-orion.h>

#include <plat/time.h>

#include <plat/common.h>

#include <plat/addr-map.h>

#include "common.h"



/*****************************************************************************
@@ -174,7 +173,8 @@ void __init orion5x_xor_init(void) 
 ****************************************************************************/

static void __init orion5x_crypto_init(void)

{

	orion5x_setup_sram_win();

	mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,

			      ORION5X_SRAM_SIZE);

	orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,

			  SZ_8K, IRQ_ORION5X_CESA);

}
@@ -193,6 +193,9 @@ void __init orion5x_wdt_init(void) 
 ****************************************************************************/

void __init orion5x_init_early(void)

{

	u32 rev, dev;

	const char *mbus_soc_name;



	orion_time_set_base(TIMER_VIRT_BASE);



	/*
@@ -201,6 +204,46 @@ void __init orion5x_init_early(void) 
	 * the allocations won't fail.

	 */

	init_dma_coherent_pool_size(SZ_1M);



	/* Initialize the MBUS driver */

	orion5x_pcie_id(&dev, &rev);

	if (dev == MV88F5281_DEV_ID)

		mbus_soc_name = "marvell,orion5x-88f5281-mbus";

	else if (dev == MV88F5182_DEV_ID)

		mbus_soc_name = "marvell,orion5x-88f5182-mbus";

	else if (dev == MV88F5181_DEV_ID)

		mbus_soc_name = "marvell,orion5x-88f5181-mbus";

	else if (dev == MV88F6183_DEV_ID)

		mbus_soc_name = "marvell,orion5x-88f6183-mbus";

	else

		mbus_soc_name = NULL;

	mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,

			ORION5X_BRIDGE_WINS_SZ,

			ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);

}



void orion5x_setup_wins(void)

{

	/*

	 * The PCIe windows will no longer be statically allocated

	 * here once Orion5x is migrated to the pci-mvebu driver.

	 */

	mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,

					  ORION5X_PCIE_IO_SIZE,

					  ORION5X_PCIE_IO_BUS_BASE,

					  MVEBU_MBUS_PCI_IO);

	mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,

					  ORION5X_PCIE_MEM_SIZE,

					  MVEBU_MBUS_NO_REMAP,

					  MVEBU_MBUS_PCI_MEM);

	mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,

					  ORION5X_PCI_IO_SIZE,

					  ORION5X_PCI_IO_BUS_BASE,

					  MVEBU_MBUS_PCI_IO);

	mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,

					  ORION5X_PCI_MEM_SIZE,

					  MVEBU_MBUS_NO_REMAP,

					  MVEBU_MBUS_PCI_MEM);

}



int orion5x_tclk;
@@ -282,7 +325,7 @@ void __init orion5x_init(void) 
	/*

	 * Setup Orion address map

	 */

	orion5x_setup_cpu_mbus_bridge();

	orion5x_setup_wins();



	/* Setup root of clk tree */

	clk_init();