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Commit 5b2d5c69 authored by Lucas Stach's avatar Lucas Stach Committed by Alex Shi
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ARM: imx6: correct i.MX6 PCIe interrupt routing 



commit 1a9fa190956f45c1e58c4d8bfa5ac051691ea590 upstream.

The PCIe interrupts are also routed through the GPC. This has been
missed from the conversion to stacked IRQ domains as the PCIe
controller uses an explicit interrupt map and thus doesn't inherit
the SoC global interrupt parent.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>

(cherry picked from commit cdda95937ec1f62e29f6e89c87600555594f3dec)
Signed-off-by: default avatarAlex Shi <alex.shi@linaro.org>
parent feb77c9d

arch/arm/boot/dts/imx6qdl.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -153,10 +153,10 @@ 
			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

			                <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,

				 <&clks IMX6QDL_CLK_LVDS1_GATE>,

				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;