Commit 5b2acf38 authored Dec 30, 2011 by Shawn Guo

ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation



The recent suspend/resume and reset testing on imx6q discovers that
not only D-Cache but also I-Cache has random data and validity when
the core comes out of a power recycle.

This patch adds I-Cache invalidation into v7_invalidate_l1 to make
sure both D-Cache and I-Cache invalidated on power-up.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

parent 5f0a6e2d

arch/arm/mach-imx/head-v7.S

+1 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,7 @@
		*/
		ENTRY(v7_invalidate_l1)
		mov r0, #0
		mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
		mcr p15, 2, r0, c0, c0, 0
		mrc p15, 1, r0, c0, c0, 0