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Commit 5b0ec2ef authored by Ralf Baechle's avatar Ralf Baechle
Browse files

Merge branch 'fixes-for-linus' into mips-for-linux-next

parents 5611cc45 3d18c983

arch/mips/ar7/platform.c

+1 −1
Original line number Diff line number Diff line
@@ -536,7 +536,7 @@ static int __init ar7_register_uarts(void) 


	bus_clk = clk_get(NULL, "bus");

	if (IS_ERR(bus_clk))

		panic("unable to get bus clk\n");

		panic("unable to get bus clk");



	uart_port.type		= PORT_AR7;

	uart_port.uartclk	= clk_get_rate(bus_clk) / 2;

arch/mips/ar7/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ void __init plat_mem_setup(void) 


	io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);

	if (!io_base)

		panic("Can't remap IO base!\n");

		panic("Can't remap IO base!");

	set_io_port_base(io_base);



	prom_meminit();

arch/mips/ath79/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ static void __init ath79_detect_sys_type(void) 
		break;



	default:

		panic("ath79: unknown SoC, id:0x%08x\n", id);

		panic("ath79: unknown SoC, id:0x%08x", id);

	}



	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);

arch/mips/bcm47xx/setup.c

+2 −2
Original line number Diff line number Diff line
@@ -289,7 +289,7 @@ static void __init bcm47xx_register_ssb(void) 
	err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,

				      bcm47xx_get_invariants);

	if (err)

		panic("Failed to initialize SSB bus (err %d)\n", err);

		panic("Failed to initialize SSB bus (err %d)", err);



	mcore = &bcm47xx_bus.ssb.mipscore;

	if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
@@ -314,7 +314,7 @@ static void __init bcm47xx_register_bcma(void) 


	err = bcma_host_soc_register(&bcm47xx_bus.bcma);

	if (err)

		panic("Failed to initialize BCMA bus (err %d)\n", err);

		panic("Failed to initialize BCMA bus (err %d)", err);

}

#endif

arch/mips/cavium-octeon/setup.c

+3 −3
Original line number Diff line number Diff line
@@ -767,11 +767,11 @@ void prom_free_prom_memory(void) 
			: "=r" (insn) : : "$31", "memory");



		if ((insn >> 26) != 0x33)

			panic("No PREF instruction at Core-14449 probe point.\n");

			panic("No PREF instruction at Core-14449 probe point.");



		if (((insn >> 16) & 0x1f) != 28)

			panic("Core-14449 WAR not in place (%04x).\n"

			      "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);

			      "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);

	}

#ifdef CONFIG_CAVIUM_DECODE_RSL

	cvmx_interrupt_rsl_enable();
@@ -779,7 +779,7 @@ void prom_free_prom_memory(void) 
	/* Add an interrupt handler for general failures. */

	if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,

			"RML/RSL", octeon_rlm_interrupt)) {

		panic("Unable to request_irq(OCTEON_IRQ_RML)\n");

		panic("Unable to request_irq(OCTEON_IRQ_RML)");

	}

#endif

}