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Commit 5a9afaaa authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Greg Kroah-Hartman
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net: ethernet: ti: cpsw: adjust cpsw fifos depth for fullduplex flow control 




[ Upstream commit 48f5bccc60675f8426a6159935e8636a1fd89f56 ]

When users set flow control using ethtool the bits are set properly in the
CPGMAC_SL MACCONTROL register, but the FIFO depth in the respective Port n
Maximum FIFO Blocks (Pn_MAX_BLKS) registers remains set to the minimum size
reset value. When receive flow control is enabled on a port, the port's
associated FIFO block allocation must be adjusted. The port RX allocation
must increase to accommodate the flow control runout. The TRM recommends
numbers of 5 or 6.

Hence, apply required Port FIFO configuration to
Pn_MAX_BLKS.Pn_TX_MAX_BLKS=0xF and Pn_MAX_BLKS.Pn_RX_MAX_BLKS=0x5 during
interface initialization.

Cc: Schuyler Patton <spatton@ti.com>
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarSasha Levin <alexander.levin@microsoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6b002c74

drivers/net/ethernet/ti/cpsw.c

+16 −0
Original line number Diff line number Diff line
@@ -293,6 +293,10 @@ struct cpsw_ss_regs { 
/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */

#define CPSW_V1_SEQ_ID_OFS_SHIFT	16



#define CPSW_MAX_BLKS_TX		15

#define CPSW_MAX_BLKS_TX_SHIFT		4

#define CPSW_MAX_BLKS_RX		5



struct cpsw_host_regs {

	u32	max_blks;

	u32	blk_cnt;
@@ -1120,11 +1124,23 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 
	switch (priv->version) {

	case CPSW_VERSION_1:

		slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);

		/* Increase RX FIFO size to 5 for supporting fullduplex

		 * flow control mode

		 */

		slave_write(slave,

			    (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |

			    CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);

		break;

	case CPSW_VERSION_2:

	case CPSW_VERSION_3:

	case CPSW_VERSION_4:

		slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);

		/* Increase RX FIFO size to 5 for supporting fullduplex

		 * flow control mode

		 */

		slave_write(slave,

			    (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |

			    CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);

		break;

	}