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Commit 58ff8d03 authored by Shaik Ameer Basha's avatar Shaik Ameer Basha Committed by Tomasz Figa
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clk: samsung: exynos5420: fix register offset for sclk_bpll 



This patch fixes the wrong register offset for sclk_bpll clock.

Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: default avatarShaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 1d87db4d

drivers/clk/samsung/clk-exynos5420.c

+1 −3
Original line number Diff line number Diff line
@@ -111,7 +111,6 @@ 
#define TOP_SPARE2		0x10b08

#define BPLL_LOCK		0x20010

#define BPLL_CON0		0x20110

#define SRC_CDREX		0x20200

#define KPLL_LOCK		0x28000

#define KPLL_CON0		0x28100

#define SRC_KFC			0x28200
@@ -204,7 +203,6 @@ static unsigned long exynos5420_clk_regs[] __initdata = { 
	GATE_TOP_SCLK_FSYS,

	GATE_TOP_SCLK_PERIC,

	TOP_SPARE2,

	SRC_CDREX,

	SRC_KFC,

	DIV_KFC0,

};
@@ -380,7 +378,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 
	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),

	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),



	MUX(0, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),

	MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),



	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),

	MUX_A(0, "mout_aclk400_mscl", mout_group1_p,