V4L/DVB (8485): v4l-dvb: remove broken PlanB driver (58cfdf9a) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/media/video/Kconfig

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		@@ -487,17 +487,6 @@ config VIDEO_PMS
		To compile this driver as a module, choose M here: the
		module will be called pms.

		config VIDEO_PLANB
		tristate "PlanB Video-In on PowerMac"
		depends on PPC_PMAC && VIDEO_V4L1 && BROKEN
		help
		PlanB is the V4L driver for the PowerMac 7x00/8x00 series video
		input hardware. If you want to experiment with this, say Y.
		Otherwise, or if you don't understand a word, say N. See
		<http://www.cpu.lu/~mlan/linux/dev/planb.html> for more info.

		Saying M will compile this driver as a module (planb).

		config VIDEO_BWQCAM
		tristate "Quickcam BW Video For Linux"
		depends on PARPORT && VIDEO_V4L1

drivers/media/video/Makefile

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		@@ -57,7 +57,6 @@ obj-$(CONFIG_VIDEO_ZORAN_DC30) += zr36050.o zr36016.o
		obj-$(CONFIG_VIDEO_ZORAN_ZR36060) += zr36060.o

		obj-$(CONFIG_VIDEO_PMS) += pms.o
		obj-$(CONFIG_VIDEO_PLANB) += planb.o
		obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o
		obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
		obj-$(CONFIG_VIDEO_CPIA) += cpia.o

drivers/media/video/planb.c

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File changed.

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drivers/media/video/planb.h

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		/*
		planb - PlanB frame grabber driver

		PlanB is used in the 7x00/8x00 series of PowerMacintosh
		Computers as video input DMA controller.

		Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)

		Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)

		Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)


		This program is free software; you can redistribute it and/or modify
		it under the terms of the GNU General Public License as published by
		the Free Software Foundation; either version 2 of the License, or
		(at your option) any later version.

		This program is distributed in the hope that it will be useful,
		but WITHOUT ANY WARRANTY; without even the implied warranty of
		MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		GNU General Public License for more details.

		You should have received a copy of the GNU General Public License
		along with this program; if not, write to the Free Software
		Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
		*/

		/* $Id: planb.h,v 1.13 1999/05/03 19:28:56 mlan Exp $ */

		#ifndef _PLANB_H_
		#define _PLANB_H_

		#ifdef __KERNEL__
		#include <asm/dbdma.h>
		#include "saa7196.h"
		#endif /* __KERNEL__ */

		#define PLANB_DEVICE_NAME "Apple PlanB Video-In"
		#define PLANB_REV "1.0"

		#ifdef __KERNEL__
		//#define PLANB_GSCANLINE /* use this if apps have the notion of */
		/* grab buffer scanline */
		/* This should be safe for both PAL and NTSC */
		#define PLANB_MAXPIXELS 768
		#define PLANB_MAXLINES 576
		#define PLANB_NTSC_MAXLINES 480

		/* Uncomment your preferred norm ;-) */
		#define PLANB_DEF_NORM VIDEO_MODE_PAL
		//#define PLANB_DEF_NORM VIDEO_MODE_NTSC
		//#define PLANB_DEF_NORM VIDEO_MODE_SECAM

		/* fields settings */
		#define PLANB_GRAY 0x1 /* 8-bit mono? */
		#define PLANB_COLOUR15 0x2 /* 16-bit mode */
		#define PLANB_COLOUR32 0x4 /* 32-bit mode */
		#define PLANB_CLIPMASK 0x8 /* hardware clipmasking */

		/* misc. flags for PlanB DMA operation */
		#define CH_SYNC 0x1 /* synchronize channels (set by ch1;
		cleared by ch2) */
		#define FIELD_SYNC 0x2 /* used for the start of each field
		(0 -> 1 -> 0 for ch1; 0 -> 1 for ch2) */
		#define EVEN_FIELD 0x0 /* even field is detected if unset */
		#define DMA_ABORT 0x2 /* error or just out of sync if set */
		#define ODD_FIELD 0x4 /* odd field is detected if set */

		/* for capture operations */
		#define MAX_GBUFFERS 2
		/* note PLANB_MAX_FBUF must be divisible by PAGE_SIZE */
		#ifdef PLANB_GSCANLINE
		#define PLANB_MAX_FBUF 0x240000 /* 576 * 1024 * 4 */
		#define TAB_FACTOR (1)
		#else
		#define PLANB_MAX_FBUF 0x1b0000 /* 576 * 768 * 4 */
		#define TAB_FACTOR (2)
		#endif
		#endif /* __KERNEL__ */

		struct planb_saa_regs {
		unsigned char addr;
		unsigned char val;
		};

		struct planb_stat_regs {
		unsigned int ch1_stat;
		unsigned int ch2_stat;
		unsigned char saa_stat0;
		unsigned char saa_stat1;
		};

		struct planb_any_regs {
		unsigned int offset;
		unsigned int bytes;
		unsigned char data[128];
		};

		/* planb private ioctls */
		#define PLANBIOCGSAAREGS _IOWR('v', BASE_VIDIOCPRIVATE, struct planb_saa_regs) /* Read a saa7196 reg value */
		#define PLANBIOCSSAAREGS _IOW('v', BASE_VIDIOCPRIVATE + 1, struct planb_saa_regs) /* Set a saa7196 reg value */
		#define PLANBIOCGSTAT _IOR('v', BASE_VIDIOCPRIVATE + 2, struct planb_stat_regs) /* Read planb status */
		#define PLANB_TV_MODE 1
		#define PLANB_VTR_MODE 2
		#define PLANBIOCGMODE _IOR('v', BASE_VIDIOCPRIVATE + 3, int) /* Get TV/VTR mode */
		#define PLANBIOCSMODE _IOW('v', BASE_VIDIOCPRIVATE + 4, int) /* Set TV/VTR mode */

		#ifdef PLANB_GSCANLINE
		#define PLANBG_GRAB_BPL _IOR('v', BASE_VIDIOCPRIVATE + 5, int) /* # of bytes per scanline in grab buffer */
		#endif

		/* call wake_up_interruptible() with appropriate actions */
		#define PLANB_INTR_DEBUG _IOW('v', BASE_VIDIOCPRIVATE + 20, int)
		/* investigate which reg does what */
		#define PLANB_INV_REGS _IOWR('v', BASE_VIDIOCPRIVATE + 21, struct planb_any_regs)

		#ifdef __KERNEL__

		/* Potentially useful macros */
		#define PLANB_SET(x) ((x) << 16 \| (x))
		#define PLANB_CLR(x) ((x) << 16)

		/* This represents the physical register layout */
		struct planb_registers {
		volatile struct dbdma_regs ch1; /* 0x00: video in */
		volatile unsigned int even; /* 0x40: even field setting */
		volatile unsigned int odd; /* 0x44; odd field setting */
		unsigned int pad1[14]; /* empty? */
		volatile struct dbdma_regs ch2; /* 0x80: clipmask out */
		unsigned int pad2[16]; /* 0xc0: empty? */
		volatile unsigned int reg3; /* 0x100: ???? */
		volatile unsigned int intr_stat; /* 0x104: irq status */
		#define PLANB_CLR_IRQ 0x00 /* clear Plan B interrupt */
		#define PLANB_GEN_IRQ 0x01 /* assert Plan B interrupt */
		#define PLANB_FRM_IRQ 0x0100 /* end of frame */
		unsigned int pad3[1]; /* empty? */
		volatile unsigned int reg5; /* 0x10c: ??? */
		unsigned int pad4[60]; /* empty? */
		volatile unsigned char saa_addr; /* 0x200: SAA subadr */
		char pad5[3];
		volatile unsigned char saa_regval; /* SAA7196 write reg. val */
		char pad6[3];
		volatile unsigned char saa_status; /* SAA7196 status byte */
		/* There is more unused stuff here */
		};

		struct planb_window {
		int x, y;
		ushort width, height;
		ushort bpp, bpl, depth, pad;
		ushort swidth, sheight;
		int norm;
		int interlace;
		u32 color_fmt;
		int chromakey;
		int mode; /* used to switch between TV/VTR modes */
		};

		struct planb_suspend {
		int overlay;
		int frame;
		struct dbdma_cmd cmd;
		};

		struct planb {
		struct video_device video_dev;
		struct video_picture picture; /* Current picture params */
		struct video_audio audio_dev; /* Current audio params */

		volatile struct planb_registers planb_base; / virt base of planb */
		struct planb_registers planb_base_phys; / phys base of planb */
		void priv_space; / Org. alloc. mem for kfree */
		int user;
		unsigned int tab_size;
		int maxlines;
		struct mutex lock;
		unsigned int irq; /* interrupt number */
		volatile unsigned int intr_mask;
		struct pci_dev dev; / Our PCI device */

		int overlay; /* overlay running? */
		struct planb_window win;
		unsigned long frame_buffer_phys; /* We need phys for DMA */
		int offset; /* offset of pixel 1 */
		volatile struct dbdma_cmd ch1_cmd; / Video In DMA cmd buffer */
		volatile struct dbdma_cmd ch2_cmd; / Clip Out DMA cmd buffer */
		volatile struct dbdma_cmd *overlay_last1;
		volatile struct dbdma_cmd *overlay_last2;
		unsigned long ch1_cmd_phys;
		volatile unsigned char mask; / Clipmask buffer */
		int suspend;
		wait_queue_head_t suspendq;
		struct planb_suspend suspended;
		int cmd_buff_inited; /* cmd buffer inited? */

		int grabbing;
		unsigned int gcount;
		wait_queue_head_t capq;
		int last_fr;
		int prev_last_fr;
		unsigned char **rawbuf;
		int rawbuf_size;
		int gbuf_idx[MAX_GBUFFERS];
		volatile struct dbdma_cmd *cap_cmd[MAX_GBUFFERS];
		volatile struct dbdma_cmd *last_cmd[MAX_GBUFFERS];
		volatile struct dbdma_cmd *pre_cmd[MAX_GBUFFERS];
		int need_pre_capture[MAX_GBUFFERS];
		#define PLANB_DUMMY 40 /* # of command buf's allocated for pre-capture seq. */
		int gwidth[MAX_GBUFFERS], gheight[MAX_GBUFFERS];
		unsigned int gfmt[MAX_GBUFFERS];
		int gnorm_switch[MAX_GBUFFERS];
		volatile unsigned int *frame_stat;
		#define GBUFFER_UNUSED 0x00U
		#define GBUFFER_GRABBING 0x01U
		#define GBUFFER_DONE 0x02U
		#ifdef PLANB_GSCANLINE
		int gbytes_per_line;
		#else
		#define MAX_LNUM 431 /* change this if PLANB_MAXLINES or */
		/* PLANB_MAXPIXELS changes */
		int l_fr_addr_idx[MAX_GBUFFERS];
		unsigned char *l_to_addr[MAX_GBUFFERS][MAX_LNUM];
		int l_to_next_idx[MAX_GBUFFERS][MAX_LNUM];
		int l_to_next_size[MAX_GBUFFERS][MAX_LNUM];
		int lsize[MAX_GBUFFERS], lnum[MAX_GBUFFERS];
		#endif
		};

		#endif /* __KERNEL__ */

		#endif /* _PLANB_H_ */

drivers/media/video/saa7196.h

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		/*
		Definitions for the Philips SAA7196 digital video decoder,
		scaler, and clock generator circuit (DESCpro), as used in
		the PlanB video input of the Powermac 7x00/8x00 series.

		Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)

		The register defines are shamelessly copied from the meteor
		driver out of NetBSD (with permission),
		and are copyrighted (c) 1995 Mark Tinguely and Jim Lowe
		(Thanks !)

		Additional debugging and coding by Takashi Oe (toe@unlinfo.unl.edu)

		The default values used for PlanB are my mistakes.
		*/

		/* $Id: saa7196.h,v 1.5 1999/03/26 23:28:47 mlan Exp $ */

		#ifndef _SAA7196_H_
		#define _SAA7196_H_

		#define SAA7196_NUMREGS 0x31 /* Number of registers (used)*/
		#define NUM_SUPPORTED_NORM 3 /* Number of supported norms by PlanB */

		/* Decoder part: */
		#define SAA7196_IDEL 0x00 /* Increment delay */
		#define SAA7196_HSB5 0x01 /* H-sync begin; 50 hz */
		#define SAA7196_HSS5 0x02 /* H-sync stop; 50 hz */
		#define SAA7196_HCB5 0x03 /* H-clamp begin; 50 hz */
		#define SAA7196_HCS5 0x04 /* H-clamp stop; 50 hz */
		#define SAA7196_HSP5 0x05 /* H-sync after PHI1; 50 hz */
		#define SAA7196_LUMC 0x06 /* Luminance control */
		#define SAA7196_HUEC 0x07 /* Hue control */
		#define SAA7196_CKTQ 0x08 /* Colour Killer Threshold QAM (PAL, NTSC) */
		#define SAA7196_CKTS 0x09 /* Colour Killer Threshold SECAM */
		#define SAA7196_PALS 0x0a /* PAL switch sensitivity */
		#define SAA7196_SECAMS 0x0b /* SECAM switch sensitivity */
		#define SAA7196_CGAINC 0x0c /* Chroma gain control */
		#define SAA7196_STDC 0x0d /* Standard/Mode control */
		#define SAA7196_IOCC 0x0e /* I/O and Clock Control */
		#define SAA7196_CTRL1 0x0f /* Control #1 */
		#define SAA7196_CTRL2 0x10 /* Control #2 */
		#define SAA7196_CGAINR 0x11 /* Chroma Gain Reference */
		#define SAA7196_CSAT 0x12 /* Chroma Saturation */
		#define SAA7196_CONT 0x13 /* Luminance Contrast */
		#define SAA7196_HSB6 0x14 /* H-sync begin; 60 hz */
		#define SAA7196_HSS6 0x15 /* H-sync stop; 60 hz */
		#define SAA7196_HCB6 0x16 /* H-clamp begin; 60 hz */
		#define SAA7196_HCS6 0x17 /* H-clamp stop; 60 hz */
		#define SAA7196_HSP6 0x18 /* H-sync after PHI1; 60 hz */
		#define SAA7196_BRIG 0x19 /* Luminance Brightness */

		/* Scaler part: */
		#define SAA7196_FMTS 0x20 /* Formats and sequence */
		#define SAA7196_OUTPIX 0x21 /* Output data pixel/line */
		#define SAA7196_INPIX 0x22 /* Input data pixel/line */
		#define SAA7196_HWS 0x23 /* Horiz. window start */
		#define SAA7196_HFILT 0x24 /* Horiz. filter */
		#define SAA7196_OUTLINE 0x25 /* Output data lines/field */
		#define SAA7196_INLINE 0x26 /* Input data lines/field */
		#define SAA7196_VWS 0x27 /* Vertical window start */
		#define SAA7196_VYP 0x28 /* AFS/vertical Y processing */
		#define SAA7196_VBS 0x29 /* Vertical Bypass start */
		#define SAA7196_VBCNT 0x2a /* Vertical Bypass count */
		#define SAA7196_VBP 0x2b /* veritcal Bypass Polarity */
		#define SAA7196_VLOW 0x2c /* Colour-keying lower V limit */
		#define SAA7196_VHIGH 0x2d /* Colour-keying upper V limit */
		#define SAA7196_ULOW 0x2e /* Colour-keying lower U limit */
		#define SAA7196_UHIGH 0x2f /* Colour-keying upper U limit */
		#define SAA7196_DPATH 0x30 /* Data path setting */

		/* Initialization default values: */

		unsigned char saa_regs[NUM_SUPPORTED_NORM][SAA7196_NUMREGS] = {

		/* PAL, 768x576 (no scaling), composite video-in */
		/* Decoder: */
		{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
		0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x06, 0x3b, 0x98,
		0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
		0xe9, 0xa2,
		/* Padding */
		0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
		/* Scaler: */
		0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
		0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
		0x87 },

		/* NTSC, 640x480? (no scaling), composite video-in */
		/* Decoder: */
		{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x50, 0x00,
		0xf8, 0xf0, 0xfe, 0xe0, 0x00, 0x06, 0x3b, 0x98,
		0x00, 0x2c, 0x3d, 0x40, 0x34, 0x0a, 0xf4, 0xd2,
		0xe9, 0x98,
		/* Padding */
		0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
		/* Scaler: */
		0x72, 0x80, 0x80, 0x03, 0x89, 0xf0, 0xf0, 0x0d,
		0xa0, 0x0d, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
		0x87 },

		/* SECAM, 768x576 (no scaling), composite video-in */
		/* Decoder: */
		{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
		0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x07, 0x3b, 0x98,
		0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
		0xe9, 0xa2,
		/* Padding */
		0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
		/* Scaler: */
		0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
		0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
		0x87 }
		};

		#endif /* _SAA7196_H_ */