Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 58aaa599 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

OMAP2+: add PRM VP functions for checking/clearing VP TX done status 



Add SoC specific PRM VP helper functions for checking and clearing
the VP transaction done status.

Longer term, these events should be handled by the forthcoming PRCM
interrupt handler.

Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
parent e74e4405

arch/arm/mach-omap2/prm2xxx_3xxx.c

+41 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 
#include <plat/cpu.h>

#include <plat/prcm.h>



#include "vp.h"



#include "prm2xxx_3xxx.h"

#include "cm2xxx_3xxx.h"

#include "prm-regbits-24xx.h"
@@ -156,3 +158,42 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) 


	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;

}



/* PRM VP */



/*

 * struct omap3_vp - OMAP3 VP register access description.

 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg

 */

struct omap3_vp {

	u32 tranxdone_status;

};



struct omap3_vp omap3_vp[] = {

	[OMAP3_VP_VDD_MPU_ID] = {

		.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,

	},

	[OMAP3_VP_VDD_CORE_ID] = {

		.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,

	},

};



#define MAX_VP_ID ARRAY_SIZE(omap3_vp);



u32 omap3_prm_vp_check_txdone(u8 vp_id)

{

	struct omap3_vp *vp = &omap3_vp[vp_id];

	u32 irqstatus;



	irqstatus = omap2_prm_read_mod_reg(OCP_MOD,

					   OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

	return irqstatus & vp->tranxdone_status;

}



void omap3_prm_vp_clear_txdone(u8 vp_id)

{

	struct omap3_vp *vp = &omap3_vp[vp_id];



	omap2_prm_write_mod_reg(vp->tranxdone_status,

				OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

}

arch/arm/mach-omap2/prm2xxx_3xxx.h

+4 −0
Original line number Diff line number Diff line
@@ -303,6 +303,10 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 
extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);

extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);



/* OMAP3-specific VP functions */

u32 omap3_prm_vp_check_txdone(u8 vp_id);

void omap3_prm_vp_clear_txdone(u8 vp_id);



#endif	/* CONFIG_ARCH_OMAP4 */

#endif

arch/arm/mach-omap2/prm44xx.c

+49 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <plat/cpu.h>

#include <plat/prcm.h>



#include "vp.h"

#include "prm44xx.h"

#include "prm-regbits-44xx.h"
@@ -50,3 +51,51 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) 


	return v;

}



/* PRM VP */



/*

 * struct omap4_vp - OMAP4 VP register access description.

 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP

 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg

 */

struct omap4_vp {

	u32 irqstatus_mpu;

	u32 tranxdone_status;

};



static struct omap4_vp omap4_vp[] = {

	[OMAP4_VP_VDD_MPU_ID] = {

		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,

		.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,

	},

	[OMAP4_VP_VDD_IVA_ID] = {

		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,

		.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,

	},

	[OMAP4_VP_VDD_CORE_ID] = {

		.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,

		.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,

	},

};



u32 omap4_prm_vp_check_txdone(u8 vp_id)

{

	struct omap4_vp *vp = &omap4_vp[vp_id];

	u32 irqstatus;



	irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,

						OMAP4430_PRM_OCP_SOCKET_INST,

						vp->irqstatus_mpu);

	return irqstatus & vp->tranxdone_status;

}



void omap4_prm_vp_clear_txdone(u8 vp_id)

{

	struct omap4_vp *vp = &omap4_vp[vp_id];



	omap4_prminst_write_inst_reg(vp->tranxdone_status,

				     OMAP4430_PRM_PARTITION,

				     OMAP4430_PRM_OCP_SOCKET_INST,

				     vp->irqstatus_mpu);

};

arch/arm/mach-omap2/prm44xx.h

+4 −0
Original line number Diff line number Diff line
@@ -751,6 +751,10 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); 
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);

extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);



/* OMAP4-specific VP functions */

u32 omap4_prm_vp_check_txdone(u8 vp_id);

void omap4_prm_vp_clear_txdone(u8 vp_id);



# endif



#endif

arch/arm/mach-omap2/vp.h

+21 −13
Original line number Diff line number Diff line
@@ -21,10 +21,28 @@ 


struct voltagedomain;



/*

 * Voltage Processor (VP) identifiers

 */

#define OMAP3_VP_VDD_MPU_ID 0

#define OMAP3_VP_VDD_CORE_ID 1

#define OMAP4_VP_VDD_CORE_ID 0

#define OMAP4_VP_VDD_IVA_ID 1

#define OMAP4_VP_VDD_MPU_ID 2



/* XXX document */

#define VP_IDLE_TIMEOUT		200

#define VP_TRANXDONE_TIMEOUT	300



/**

 * struct omap_vp_ops - per-VP operations

 * @check_txdone: check for VP transaction done

 * @clear_txdone: clear VP transaction done status

 */

struct omap_vp_ops {

	u32 (*check_txdone)(u8 vp_id);

	void (*clear_txdone)(u8 vp_id);

};



/**

 * struct omap_vp_common_data - register data common to all VDDs
@@ -68,41 +86,31 @@ struct omap_vp_common_data { 
	u8 vlimitto_vddmin_shift;

	u8 vlimitto_vddmax_shift;

	u8 vlimitto_timeout_shift;

};



/**

 * struct omap_vp_prm_irqst_data - PRM_IRQSTATUS_MPU.VP_TRANXDONE_ST data

 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg

 *

 * XXX Note that on OMAP3, VP_TRANXDONE interrupt may not work due to a

 *     hardware bug

 * XXX This structure is probably not needed

 */

struct omap_vp_prm_irqst_data {

	u32 tranxdone_status;

	const struct omap_vp_ops *ops;

};



/**

 * struct omap_vp_instance_data - VP register offsets (per-VDD)

 * @vp_common: pointer to struct omap_vp_common_data * for this SoC

 * @prm_irqst_data: pointer to struct omap_vp_prm_irqst_data for this VDD

 * @vpconfig: PRM_VP*_CONFIG reg offset from PRM start

 * @vstepmin: PRM_VP*_VSTEPMIN reg offset from PRM start

 * @vlimitto: PRM_VP*_VLIMITTO reg offset from PRM start

 * @vstatus: PRM_VP*_VSTATUS reg offset from PRM start

 * @voltage: PRM_VP*_VOLTAGE reg offset from PRM start

 * @id: Unique identifier for VP instance.

 *

 * XXX vp_common is probably not needed since it is per-SoC

 */

struct omap_vp_instance_data {

	const struct omap_vp_common_data *vp_common;

	const struct omap_vp_prm_irqst_data *prm_irqst_data;

	u8 vpconfig;

	u8 vstepmin;

	u8 vstepmax;

	u8 vlimitto;

	u8 vstatus;

	u8 voltage;

	u8 id;

};



/**