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Commit 58170f3b authored by Rajesh Bondugula's avatar Rajesh Bondugula Committed by Matt Wagantall
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ARM: dts: msm: Update PHY clock in msm8996 camera dtsi 



Update PHY clock to 200 Mhz from 266 Mhz.
200Mhz clock is sufficient for the current data rate.
Also using lower clock rate saves power.

Change-Id: Ifdd3ee1c5e080758fa118d7eaa6363503781d2a6
Signed-off-by: default avatarRajesh Bondugula <rajeshb@codeaurora.org>
parent fa5ee530

arch/arm/boot/dts/qcom/msm8996-camera.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
			"ispif_ahb_clk", "csiphy_timer_src_clk",

			"csiphy_timer_clk", "camss_ahb_clk",

			"csiphy_3p_clk_src", "csi_phy_3p_clk";

		qcom,clock-rates = <0 0 266666667 0 0 100000000 0>;

		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;

	};



	qcom,csiphy@a35000 {
@@ -58,7 +58,7 @@ 
			"ispif_ahb_clk", "csiphy_timer_src_clk",

			"csiphy_timer_clk", "camss_ahb_clk",

			"csiphy_3p_clk_src", "csi_phy_3p_clk";

		qcom,clock-rates = <0 0 266666667 0 0 100000000 0>;

		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;

	};



	qcom,csiphy@a36000 {
@@ -79,7 +79,7 @@ 
			"ispif_ahb_clk", "csiphy_timer_src_clk",

			"csiphy_timer_clk", "camss_ahb_clk",

			"csiphy_3p_clk_src", "csi_phy_3p_clk";

		qcom,clock-rates = <0 0 266666667 0 0 100000000 0>;

		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;

	};



	qcom,csid@a30000  {